Xilinx KC705 User Manual page 86

Appendix C: Master Board Constraints
set_property PACKAGE_PIN D14 [get_ports FMC_HPC_HA06_P]
set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA06_P]
set_property PACKAGE_PIN C14 [get_ports FMC_HPC_HA06_N]
set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA06_N]
set_property PACKAGE_PIN B13 [get_ports FMC_HPC_HA11_P]
set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA11_P]
set_property PACKAGE_PIN A13 [get_ports FMC_HPC_HA11_N]
set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA11_N]
set_property PACKAGE_PIN C15 [get_ports FMC_HPC_HA12_P]
set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA12_P]
set_property PACKAGE_PIN B15 [get_ports FMC_HPC_HA12_N]
set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA12_N]
set_property PACKAGE_PIN B14 [get_ports FMC_HPC_HA07_P]
set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA07_P]
set_property PACKAGE_PIN A15 [get_ports FMC_HPC_HA07_N]
set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA07_N]
set_property PACKAGE_PIN F16 [get_ports GPIO_LED_7_LS]
set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_7_LS]
set_property PACKAGE_PIN Y14 [get_ports PMBUS_DATA_LS]
set_property IOSTANDARD LVCMOS15 [get_ports PMBUS_DATA_LS]
set_property PACKAGE_PIN AK16 [get_ports DDR3_D24]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D24]
set_property PACKAGE_PIN AK15 [get_ports DDR3_D31]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D31]
set_property PACKAGE_PIN AG15 [get_ports DDR3_D26]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D26]
set_property PACKAGE_PIN AH15 [get_ports DDR3_D30]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D30]
set_property PACKAGE_PIN AH16 [get_ports DDR3_DQS3_P]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS3_P]
set_property PACKAGE_PIN AJ16 [get_ports DDR3_DQS3_N]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS3_N]
set_property PACKAGE_PIN AF15 [get_ports DDR3_D27]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D27]
set_property PACKAGE_PIN AG14 [get_ports DDR3_D29]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D29]
set_property PACKAGE_PIN AH17 [get_ports DDR3_D28]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D28]
set_property PACKAGE_PIN AJ17 [get_ports DDR3_D25]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D25]
set_property PACKAGE_PIN AE16 [get_ports DDR3_DM3]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM3]
set_property PACKAGE_PIN AF16 [get_ports VTTVREF]
set_property PACKAGE_PIN AJ19 [get_ports DDR3_D21]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D21]
set_property PACKAGE_PIN AK19 [get_ports DDR3_D17]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D17]
set_property PACKAGE_PIN AG19 [get_ports DDR3_D16]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D16]
set_property PACKAGE_PIN AH19 [get_ports DDR3_D20]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D20]
set_property PACKAGE_PIN AJ18 [get_ports DDR3_DQS2_P]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS2_P]
set_property PACKAGE_PIN AK18 [get_ports DDR3_DQS2_N]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS2_N]
set_property PACKAGE_PIN AD19 [get_ports DDR3_D23]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D23]
set_property PACKAGE_PIN AE19 [get_ports DDR3_D22]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D22]
set_property PACKAGE_PIN AF18 [get_ports DDR3_D19]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D19]
set_property PACKAGE_PIN AG18 [get_ports DDR3_D18]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D18]
set_property PACKAGE_PIN AF17 [get_ports DDR3_DM2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM2]
set_property PACKAGE_PIN AG17 [get_ports PMBUS_CLK_LS]
set_property IOSTANDARD LVCMOS15 [get_ports PMBUS_CLK_LS]
set_property PACKAGE_PIN AD18 [get_ports DDR3_D15]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D15]
set_property PACKAGE_PIN AE18 [get_ports DDR3_D14]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D14]
set_property PACKAGE_PIN AD17 [get_ports DDR3_D11]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D11]
set_property PACKAGE_PIN AD16 [get_ports DDR3_D9]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D9]
set_property PACKAGE_PIN Y19 [get_ports DDR3_DQS1_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS1_P]
set_property PACKAGE_PIN Y18 [get_ports DDR3_DQS1_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS1_N]
set_property PACKAGE_PIN AA18 [get_ports DDR3_D12]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D12]
86 www.xilinx.com KC705 Evaluation Board
UG810 (v1.4) July 18, 2013