Xilinx KC705 User Manual page 87

set_property PACKAGE_PIN AB18 [get_ports DDR3_D13]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D13]
set_property PACKAGE_PIN AB19 [get_ports DDR3_D8]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D8]
set_property PACKAGE_PIN AC19 [get_ports DDR3_D10]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D10]
set_property PACKAGE_PIN AB17 [get_ports DDR3_DM1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM1]
set_property PACKAGE_PIN AC17 [get_ports 7N700]
set_property PACKAGE_PIN AE15 [get_ports DDR3_D6]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D6]
set_property PACKAGE_PIN AE14 [get_ports VTTVREF]
set_property PACKAGE_PIN AA15 [get_ports DDR3_D0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D0]
set_property PACKAGE_PIN AB15 [get_ports DDR3_D5]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D5]
set_property PACKAGE_PIN AC16 [get_ports DDR3_DQS0_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS0_P]
set_property PACKAGE_PIN AC15 [get_ports DDR3_DQS0_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS0_N]
set_property PACKAGE_PIN AC14 [get_ports DDR3_D2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D2]
set_property PACKAGE_PIN AD14 [get_ports DDR3_D3]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D3]
set_property PACKAGE_PIN AA17 [get_ports DDR3_D4]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D4]
set_property PACKAGE_PIN AA16 [get_ports DDR3_D1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D1]
set_property PACKAGE_PIN Y16 [get_ports DDR3_DM0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM0]
set_property PACKAGE_PIN Y15 [get_ports DDR3_D7]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D7]
set_property PACKAGE_PIN AB14 [get_ports PMBUS_ALERT_LS]
set_property IOSTANDARD LVCMOS15 [get_ports PMBUS_ALERT_LS]
set_property PACKAGE_PIN Y13 [get_ports VRN_33]
set_property IOSTANDARD SSTL15 [get_ports VRN_33]
set_property PACKAGE_PIN AA12 [get_ports GPIO_SW_N]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_SW_N]
set_property PACKAGE_PIN AB12 [get_ports GPIO_SW_S]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_SW_S]
set_property PACKAGE_PIN AA8 [get_ports GPIO_LED_1_LS]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_1_LS]
set_property PACKAGE_PIN AB8 [get_ports GPIO_LED_0_LS]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_0_LS]
set_property PACKAGE_PIN AB9 [get_ports GPIO_LED_3_LS]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_3_LS]
set_property PACKAGE_PIN AC9 [get_ports GPIO_LED_2_LS]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_2_LS]
set_property PACKAGE_PIN Y11 [get_ports LCD_RS_LS]
set_property IOSTANDARD LVCMOS15 [get_ports LCD_RS_LS]
set_property PACKAGE_PIN Y10 [get_ports LCD_DB7_LS]
set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB7_LS]
set_property PACKAGE_PIN AA11 [get_ports LCD_DB6_LS]
set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB6_LS]
set_property PACKAGE_PIN AA10 [get_ports LCD_DB5_LS]
set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB5_LS]
set_property PACKAGE_PIN AA13 [get_ports LCD_DB4_LS]
set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB4_LS]
set_property PACKAGE_PIN AB13 [get_ports LCD_RW_LS]
set_property IOSTANDARD LVCMOS15 [get_ports LCD_RW_LS]
set_property PACKAGE_PIN AB10 [get_ports LCD_E_LS]
set_property IOSTANDARD LVCMOS15 [get_ports LCD_E_LS]
set_property PACKAGE_PIN AC10 [get_ports DDR3_ODT1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT1]
set_property PACKAGE_PIN AD8 [get_ports DDR3_ODT0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT0]
set_property PACKAGE_PIN AE8 [get_ports DDR3_S1_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_S1_B]
set_property PACKAGE_PIN AC12 [get_ports DDR3_S0_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_S0_B]
set_property PACKAGE_PIN AC11 [get_ports DDR3_CAS_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_CAS_B]
set_property PACKAGE_PIN AD9 [get_ports DDR3_RAS_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_RAS_B]
set_property PACKAGE_PIN AE9 [get_ports DDR3_WE_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_WE_B]
set_property PACKAGE_PIN AE11 [get_ports DDR3_CLK1_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK1_P]
set_property PACKAGE_PIN AF11 [get_ports DDR3_CLK1_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK1_N]
set_property PACKAGE_PIN AD12 [get_ports SYSCLK_P]
KC705 Evaluation Board
UG810 (v1.4) July 18, 2013
www.xilinx.com
KC705 Board XDC Listing
87