Analog Devices ADSP-BF707 EZ-KIT Lite Manual page 82

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I INDEX
A
ADSP-BF707 processor, x
architecture, of this EZ-KIT Lite,
B
bill of materials, A-1
board schematic (ADSP-BF707),
boot mode select switch (SW1),
bus switch, 2-5
example, 2-6
C
CAN0 connector (J4), 2-24
CAN0 interface, 1-10
CAN1 connector (J5), 2-25
CAN1 interface, 1-11
configuration, of this EZ-KIT Lite,
connectors, 2-21
diagram of locations, 2-21
J3 (RF wireless), 2-23
J4 (CAN0), 2-24
J5 (CAN1), 2-25
J6 (SD), 2-24
J7, J8, J9 (HADC SMC), 2-23
JP1 (HADC), 2-24
P13 (power), 2-22
P1A-C (expansion interface III),
P2 (TRACE and JTAG/SWD/SWO),
P3 (JTAG/SWD/SWO), 2-25
ADSP-BF707 EZ-KIT Lite Evaluation System Manual
connectors
P5 (USB),
P6 (USB to UART),
2-2
contents, of this EZ-KIT Lite package,
D
DDR2 memory,
B-1
debug interface,
2-17
default configuration, of this EZ-KIT Lite,
default jumper and switch settings,
default processor interface availability,
design reference information,
E
EngineerZone,
evaluation license,
example programs,
1-3
expansion interface,
expansion interface III connectors (P1A-C),
2-22
F
FET switches,
example, 2-4
G
2-22
2-25 general-purpose I/O pins (GPIO),
GPIO LEDs (LED3-5),
GPIO push buttons switches (SW3-4),
(continued)
2-23
2-22
1-2
1-8
1-12
1-4
2-7
1-15
xvii
1-8
1-14
1-13
2-4
2-20
2-20
2-17
1-3
I-1