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SD Interface
SD Interface
Debug Interface
Power-On-Self Test
1-12
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The ADSP-BF707 processor has a secure digital (SD) interface that con-
sists of a clock pin, command pin, card detect pin, and an 8-bit data bus.
SoftConfig controls the connection of the card detect pin (
GPIO pin used for write protect (
Switches (SoftConfig)
and
An example program is included in the ADSP-BF707 Board Support
Package.
The EZ-KIT Lite provides a JTAG/SWD/SWO connection via connector
(
), which is a 0.05" pitch header. An 8-bit trace connection also is avail-
P3
able via connector (
), although this is not supported at this time. See
P2
JTAG/SWD/SWO Connector (P3)
Connector (P2)
for more information.
The Power-On-Self-Test Program (POST) tests all EZ-KIT Lite peripher-
als and validates functionality as well as connectivity to the processor.
Once assembled, each EZ-KIT Lite is fully tested for an extended period
of time with POST. All EZ-KIT Lite boards are shipped with POST pre-
loaded into flash memory. The POST is executed by resetting the board
and pressing the proper push button(s). The POST also can be used as a
reference for a custom software design or hardware troubleshooting.
Note that the source code for the POST program is included in the
ADSP-BF707 Board Support Package along with the
describes how the board is configured to run POST.
ADSP-BF707 EZ-KIT Lite Evaluation System Manual
). Refer to
Software-Controlled
PB_07
SD Connector (J6)
for more details.
and
TRACE and JTAG/SWD/SWO
) and a
PA_08
file that
readme.txt
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