AXIOMTEK CAPA13S User Manual page 68

CAPA13S Capa Board
Register 0: Input port register.
This register is a read-only port. It reflects the incoming logic levels of the pins, regardless of
whether the pin is defined as an input or an output by Register 3. Writes to this register have
no effect.
The default "X" is determined by the externally applied logic level, normally "1" when no
external signal externally applied because of the internal pull-up resistors.
Register 0 – Input port register bit description
Bit Symbol
7 I7
6 I6
5 I5
4 I4
3 I3
2 I2
1 I1
0 I0
Register 1: Output port register.
This register reflects the outgoing logic levels of the pins defined as outputs by Register 3. Bit
values in this register have no effect on pins defined as inputs. Reads from this register return
the value that is in the flip-flop controlling the output selection, not the actual pin value.
Register 1 – Output port register bit description
Bit Symbol Access
7 O7 R
6 O6 R
5 O5 R
4 O4 R
3 O3 R
2 O2 R
1 O1 R
0 O0 R
Register 2: Polarity Inversion register.
This register allows the user to invert the polarity of the Input port register data. If a bit in this
register is set (written with "1"), the corresponding Input port data is inverted. If a bit in this
register is cleared (written with "0"), the Input port data polarity is retained.
Register 2 – Polarity inversion register bit description
Bit Symbol Access
7 N7 R/W
6 N6 R/W
5 N5 R/W
4 N4 R/W
3 N3 R/W
2 N2 R/W
1 N1 R/W
0 N0 R/W
62
Access Value
Read only X
Read only X
Read only X
Read only X
Read only X
Read only X
Read only X
Read only X
Default Value
1
1
1
1
1
1
1
1
Default Value
0
0
0
0
0
0
0
0
Description
Determined by externally applied
logic level.
Description
Reflects outgoing logic levels of pins defined as
outputs by Register 3.
Description
Inverts polarity of Input port register data.
0 = Input port register data retained (default
value).
1 = Input port register data inverted.
Digital I/O