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Common to "with wait" and "no-wait" (actual MCU)
BCLK
HOLD input
HLDA output
P0, P1, P2,
P3, P4,
P5
to P5
0
2
Common to "with wait" and "no-wait" (This product)
BCLK
HOLD input
HLDA output
P0, P1, P2,
P3, P4,
P5
to P5
0
2
Note 1. Ports P0
to P5
0
and ports P4
Note 2. This product will be high-impedance status delaying by 2.5 cycles than an actual MCU.
Note 3. The setup time of HOLD is defined by the startup of BCLK, differently from that of actual
MCUs.
Figure 5.5 Timing requirements
will be high-impedance status regardless of the input level of BYTE pin
2
to P4
function selection bit (PM06) of the processor mode register 0.
0
3
( 60 / 76 )
Conditions:
• V
= 5 V
CC
• Input timing voltage: V
IL
• Output timing voltage: V
= 1.0 V, V
= 4.0 V
IH
= 2.5 V, V
= 2.5 V
OL
OH
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