B.8.4 Emvl-Pgs01 - Delta Electronics Elevator Drive VFD-VL User Manual

Appendix B Accessories|
that B leads A. A-/A is a square wave input. B/O-/B/O and B-/B should be input
synchronously. A/O-/A/O is the output of frequency divider.
Z/O-/Z/O of the PG card will act by the input signal of Z-/Z and don't have the function of
frequency divider.
When changing the denominator of the frequency divider or input/output type, it needs to
clear the counter value by clock reset bit (PIN4) before operation. Please set the switch to
1 after reset.

B.8.4 EMVL-PGS01

Applicable encoders for EMVL-PGS01:
EnDat2.1: EQN425, EQN1325, ECN113, ECN413, ECN1113, ECN1313
HIPERFACE: SRS50/60
1. Pin description
5
10
15 14 13 12 11
B-32
VFD-VL Series
4
3 1
2
9 8 7 6
VFD-VL Series
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Corresponding terminal
EnDat HIPERFACE®
B- REFSIN
0V
0V
0V
A+ +COS
A- REFCOS
0V
B+ +SIN
VP
Data+ Data+
Data- Data-
CLOCK+
CLOCK-
VP
0V
Revision Nov. 2008, VLE1, SW V1.03
0V
0V
0V
0V
VP
-
-
VP
0V