Delta Electronics Elevator Drive VFD-VL User Manual page 224

4. Output Signal Setting of the Frequency Divider
It generates the output signal of division factor
"n" after dealing with the input pulse. Please
set by the switch SW1 on the card.
ON
0
1
3 4 5 6 7 8 9 10 11 12
1 2
Settings and explanations
X 0 0 1
X 0 1 1
X 1 X 1
Revision Nov. 2008, VLE1, SW V1.03
Division Factor
A leads B
A-/A
B-/B
A/O-/A/O
B/O-/B/O
A-/A
B-/B
A/O-/A/O A/O-/A/O
B/O-/B/O B/O-/B/O
A-/A
B-/B
A/O-/A/O A/O-/A/O
B/O-/B/O B/O-/B/O
Appendix B Accessories|
RESERVE: reserved bit (PIN1)
I/MODE: input type setting of the division
pulse (PIN 2)
O/MODE: output type setting of the division
pulse (PIN 3)
RST: clock reset bit (PIN 4)
Division factor: setting for division factor n:
1~256 (PIN5~12)
Division factor
B leads A
A-/A
B-/B
A/O-/A/O A/O-/A/O
B/O-/B/O B/O-/B/O
A-/A
B-/B
A/O-/A/O A/O-/A/O
B/O-/B/O B/O-/B/O
A-/A
B-/B
A/O-/A/O A/O-/A/O
B/O-/B/O B/O-/B/O
B-27