Serial Port Control Register (Spcr); Serial Port Control Register (Spcr) Field Descriptions - Texas Instruments TMS320DM36 Series User Manual

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3.3

Serial Port Control Register (SPCR)

The serial port is configured via the serial port control register (SPCR) and the pin control register (PCR).
The SPCR contains McBSP status control bits. The SPCR is shown in
Table 28.
31
23 22
FRST GRST
R/W-0 R/W-0
15 14
DLB RJUST
R/W-0
7 6
DXENA Reserved
R/W-0 R-0
LEGEND: R = Read only; R/W = Read/ Write; -n = value after reset
Bit Field Value
31-26 Reserved 0
25 FREE
0
1
24 SOFT
0
1
23 FRST
0
1
22 GRST
0
1
21-20 XINTM 0-3h
0
1h
2h
3h
SPRUFI3A – March 2009 – Revised August 2009
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Figure 49. Serial Port Control Register (SPCR)
Reserved
R-0
21
XINTM
R/W-0
13 12
R/W-0
5
RINTM
R/W-0
Table 28. Serial Port Control Register (SPCR) Field Descriptions
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Free-running enable mode bit. This bit is used in conjunction with SOFT bit to determine state of serial
port clock during emulation halt.
Free-running mode is disabled. During emulation halt, SOFT bit determines operation of McBSP.
Free-running mode is enabled. During emulation halt, serial clocks continue to run.
Soft bit enable mode bit. This bit is used in conjunction with FREE bit to determine state of serial port
clock during emulation halt. This bit has no effect if FREE = 1.
Soft mode is disabled. Serial port clock stops immediately during emulation halt, thus aborting any
transmissions.
Soft mode is enabled. During emulation halt, serial port clock stops after completion of current
transmission.
Frame-sync generator reset bit.
Frame-synchronization logic is reset. Frame-sync signal (FSG) is not generated by the sample-rate
generator.
Frame-sync signal (FSG) is generated after (FPER + 1) number of CLKG clocks; that is, all frame
counters are loaded with their programmed values.
Sample-rate generator reset bit.
Sample-rate generator is reset.
Sample-rate generator is taken out of reset. CLKG is driven as per programmed value in sample-rate
generator register (SRGR).
Transmit interrupt (XINT) mode bit.
XINT is driven by XRDY (end-of-word).
Reserved
XINT is generated by a new frame synchronization.
XINT is generated by XSYNCERR.
Copyright © 2009–2009, Texas Instruments Incorporated
20 19 18
XSYNCERR XEMPTY
R/W-0 R-0
11 10
CLKSTP
R-0
4 3 2
RSYNCERR RFULL
R/W-0 R-0
TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface
Figure 49 and described in
26 25
FREE
R/W-0
17
XRDY
R-0
Reserved
1
RRDY
R-0
Registers
24
SOFT
R/W-0
16
XRST
R/W-0
8
0
RRST
R/W-0
69