Texas Instruments TMS320DM36 Series User Manual
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Texas Instruments TMS320DM36 Series User Manual

Texas Instruments TMS320DM36 Series User Manual

Digital media system-on-chip dmsoc power management and real-time clock subsystem prtcss
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TMS320DM36x Digital Media System-on-Chip
(DMSoC) Power Management and Real-Time
Clock Subsystem (PRTCSS)
User's Guide
Literature Number: SPRUFJ0A
May 2009 – Revised March 2010

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Summary of Contents for Texas Instruments TMS320DM36 Series

  • Page 1 TMS320DM36x Digital Media System-on-Chip (DMSoC) Power Management and Real-Time Clock Subsystem (PRTCSS) User's Guide Literature Number: SPRUFJ0A May 2009 – Revised March 2010...
  • Page 2 SPRUFJ0A – May 2009 – Revised March 2010 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 3: Table Of Contents

    3.3.2.3 Initializing the Calendar with Alarm ......................Sequencer ..................3.4.1 Sequencer Features ..............3.4.2 Initial Sequencer Flow in Normal Mode SPRUFJ0A – May 2009 – Revised March 2010 Table of Contents Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...
  • Page 4 RTC Days[14:8] Alarm (RTC_ADAY1) Register ..............4.2.28 Clock Control (CLKC_CNT) Register ..........4.2.29 Sequencer Loop Counter Value (SEQ_LOOP) Register ...................... Appendix A Revision History Contents SPRUFJ0A – May 2009 – Revised March 2010 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...
  • Page 5 RTC Days[7:0] Alarm (RTC_ADAY0) Register ............... RTC Days[14:8] Alarm (RTC_ADAY1) Register .................. Clock Control (CLKC_CNT) Register ............. Sequencer Loop Counter Value (SEQ_LOOP) Register SPRUFJ0A – May 2009 – Revised March 2010 List of Figures Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...
  • Page 6 ................ Clock Control (CLKC_CNT) Field Descriptions ..........Sequencer Loop Counter Value (SEQ_LOOP) Field Descriptions ..................Changes Made in This Revision List of Tables SPRUFJ0A – May 2009 – Revised March 2010 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 7: Preface

    DMSoC and external peripherals. Typical applications include an interface to external I/O or peripheral expansion via devices such as shift registers, display drivers, SPI EPROMs and analog-to-digital converters. SPRUFJ0A – May 2009 – Revised March 2010 Preface Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...
  • Page 8 (UHPI) User's Guide This document describes the operation of the universal host port interface in the TMS320DM36x Digital Media System-on-Chip (DMSoC). Read This First SPRUFJ0A – May 2009 – Revised March 2010 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...
  • Page 9 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Face Detection User's GuideThis document describes the face detection capabilities for the TMS320DM36x Digital Media System-on-Chip (DMSoC). SPRUFJ0A – May 2009 – Revised March 2010 Read This First Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 10: Purpose Of The Prtc Subsystem

    PWRST Input Reset signal for PRTCSS PWRCNTON Input Reset pin for system power sequencing TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 11: Configuration Of Prtcss And Prtcif

    PRTCSS calendar/RTC contents will be retained even when the DM36x is reset. In this case, the PRTCSS submodule must be battery-powered. SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 12: Prtcss Initialization Sequence In Normal Mode

    Wait the WDT event for the D 36x OSC D 36x has to Stop WDT. TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 13: External Reset Mode

    Subsystem User's Guide (SPRUFG5). The CLKC_CNT register is used to set WDT and Peripheral Clocks divider values. SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 14: Clock Controller

    Enable the desired interrupts, if any, in the PRTCIF interrupt enable register (PRTCIF_INTEN) • If DIR is 1, then: TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 15: Flow Of The Prtcif Function

    Flow of the PRTCIF Function Figure 5 shows the flow of the PRTCIF function. SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 16: Interrupt Status Of Prtcss Events

    PRTCIF_INT_FLAG = 1 in the PRTCIF Interrupt Flag Register (PRTCIF_INTFLG) indicates the end of DMA access to PRTCSS from PRTCIF TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 17: Power Management

    Information on any signals using open-drain outputs is available in the device data manual. SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 18: Configuring Gio Interrupt Edge Triggering

    DTH = 00 DTH = 01 DTH = 02 DTH = 03 DTH = 04 DTH = 05 DTH = 06 DTH = 07 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 19: Prtcss Intc

    The PRTCSS module outputs a single interrupt RTCINT that is routed to the DM36x interrupt controller. The INTC supports interrupts from GIO signals and interrupts from RTC signals. SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 20: Configuring The Intc Interrupt

    RTC Functional Block Diagram The RTC module functional block diagram is shown in Figure TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 21: Rtc Initialization

    After countdown period = TMR[15:0]/Clk_Peri, set the TMRFLG bit in the RTC_CTRL register to enable the timer interrupt to occur. SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 22: Initializing The Watchdog Timer

    RTC alarm enable bits configuration for the alarm interrupt and Figure 8 illustrates the diagram for alarm interrupt. TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 23: Sequencer

    The sequencer module drives the PWCTRO1 and PWCTRO0 pins to control the power on/off and reset for the DM36x device. SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 24: Initial Sequencer Flow In Normal Mode

    Power Off Set PWCTRO0 0 Sequence Reset On Power Off Set PWCTRO1 0 Stop TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 25: Registers

    PRTCIF interrupt enable register Section 4.1.5 0x14 PRTCIF_INTFLG PRTCIF interrupt flag register Section 4.1.6 SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 26: Prtcif Peripheral Id (Pid) Register

    Table 6. PRTCIF Peripheral ID Register (PID) Field Descriptions Field Value Description 31-0 Peripheral ID TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 27: Prtcif Control (Prtcif_Ctrl) Register

    Any writes to these bit(s) must always have a value of 0. ADRS PRTCSS target memory address SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 28: Prtcif Access Lower Data (Prtcif_Ldata) Register

    Table 8. PRTCIF Access Lower Data (PRTCIF_LDATA) Field Descriptions Field Value Description 31-0 PRTCIF access data for lower 4 bytes TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 29: Prtcif Access Upper Data (Prtcif_Udata) Register

    Table 9. PRTCIF Access Upper Data (PRTCIF_UDATA) Field Descriptions Field Value Description 31-0 PRTCIF access data for upper 4 bytes SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 30: Prtcif Interrupt Enable (Prtcif_Inten) Register

    Any writes to these bit(s) must always have a value of 0. PRTCSS_INT_EN PRTCSS interrupt enable PRTCIF_INT_EN PRTCIF interrupt enable TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 31: Prtcif Interrupt Flag (Prtcif_Intflg) Register

    PRTCSS interrupt flag. Cleared by writing 1. PRTCIF_INT_FLAG PRTCIF interrupt flag. Cleared by writing 1. SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 32: Power Management And Real Time Clock Subsystem (Prtcss) Registers

    Section 4.2.27 0x1F-0x1E Reserved Reserved 0x20 CLKC_CNT Clock control register Section 4.2.28 0x21-0x31 Reserved Reserved TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 33: Global Output Pin Output Data (Go_Out) Register

    PWCTRO output data PWCTRO pin n is driven low PWCTRO pin n is driven high SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 34: Global Input/Output Pin Output Data (Gio_Out) Register

    PWCTRIO output data PWCTRIO pin n is driven low PWCTRIO pin n is driven high TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 35: Global Input/Output Pin Direction (Gio_Dir) Register

    This bit is used to control the direction of pin n. PWCTRIO pin n is an output PWCTRIO pin n is an input SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 36: Global Input/Output Pin Input Data (Gio_In) Register

    PWCTRIO input data PWCTRIO pin n is logic low PWCTRIO pin n is logic high TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 37: Global Input/Output Pin Function (Gio_Func) Register

    Function enable PWCTRO function 32.768 kHz clockout function PWM output (Polarity=0) PWM output (Polarity=1) SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 38: Gio Rise Interrupt Enable (Gio_Rise_Int_En) Register

    Enable rising edge interrupt detection on PWCTRIO pin n No effect Generate interrupt for the rise edge TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 39: Gio Fall Interrupt Enable (Gio_Fall_Int_En) Register

    Enable falling edge interrupt detection on PWCTRIO pin n No effect Generate interrupt for the fall edge SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 40: Gio Rise Interrupt Flag (Gio_Rise_Int_Flg) Register

    Interrupt flag register for rising edge for PWCTRIO pin n; cleared by writing 1. TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 41: Gio Fall Interrupt Flag (Gio_Fall_Int_Flg) Register

    Interrupt flag register for falling edge for PWCTRIO pin n; cleared by writing 1. SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 42: Ext Interrupt Enable 0 (Intc_Extena0) Register

    Disable Enable PWCTRIO1 PWCTRIO1 interrupt enable Disable Enable PWCTRIO0 PWCTRIO0 interrupt enable Disable Enable TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 43: Ext Interrupt Enable 1 (Intc_Extena1) Register

    Alarm interrupt enable for DM36x main device Disable Enable WDT interrupt enable for DM36x main device Disable Enable SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 44: Event Interrupt Flag 0 (Intc_Flg0) Register

    PWCTRIO1 PWCTRIO1 interrupt flag No interrupt Interrupt PWCTRIO0 PWCTRIO0 interrupt flag No interrupt Interrupt TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 45: Event Interrupt Flag 1 (Intc_Flg1) Register

    ALARM Alarm interrupt flag No interrupt interrupt WDT interrupt flag No interrupt interrupt SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 46: Rtc Control (Rtc_Ctrl) Register

    To run the timer in one-shot/free-run mode after an interrupt occurs, the timer interrupt flag (TMRFLG) should be cleared in advance. TMMD Timer run mode One-shot Free-run TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 47: Watchdog Timer Counter (Rtc_Wdt) Register

    Countdown period = WDT/ WDT peripheral clock frequency WDT peripheral clock frequency (Clk_WDT) = 32.768 kHz / CLKC_WDT SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 48: Timer Counter 0 (Rtc_Tmr0) Register

    Table 28. Timer Counter 0 (RTC_TMR0) Field Descriptions Field Value Description TMR[7:0] Timer counter value [7:0] TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 49: Timer Counter 1 (Rtc_Tmr1) Register

    Countdown period = TMR[15:0]/ timer peripheral clock frequency Timer peripheral clock frequency (Clk_Peri) = 32.768 kHz / CLKC_PERI SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 50: Rtc Calendar Control (Rtc_Cctrl) Register

    No interrupt Interrupt AIEN Alarm interrupt enable Disable Enable CAEN Calendar enable Disable Enable TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 51: Rtc Seconds (Rtc_Sec) Register

    If 59 seconds are set to SEC, then SEC will become 7'b1011001. When the value is written to this register, the counter of less than one second is cleared. SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 52: Rtc Minutes (Rtc_Min) Register

    Minutes 00 to 59 coded in BCD. If 59 minutes are set to MIN, then MIN will become 7'b1011001. TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 53: Rtc Hours (Rtc_Hour) Register

    Hours 00 to 23 coded in BCD. If 23 hours are set to HOUR, then HOUR will become 6'b100011. SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 54: Rtc Days[7:0] (Rtc_Day0) Register

    Table 34. RTC Days[7:0] (RTC_DAY0) Field Descriptions Field Value Description DAY[7:0] Days counter [7:0] TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 55: Rtc Days[14:8] (Rtc_Day1) Register

    For reading and writing the calendar value, access calendar registers in the following order : RTC_SEC -> RTC_MIN -> RTC_HOUR -> RTC_DAY0 -> RTC_DAY1 SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 56: Rtc Minutes Alarm (Rtc_Amin) Register

    Minutes alarm 00 to 59 coded in BCD. If 59 minutes are set to AMIN, then AMIN will become 7'b1011001. TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 57: Rtc Hours Alarm (Rtc_Ahour) Register

    Hours alarm 00 to 23 coded in BCD. If 23 hours are set to AHOUR, then AHOUR will become 6'b100011. SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 58: Rtc Days[7:0] Alarm (Rtc_Aday0) Register

    Table 38. RTC Days[7:0] Alarm (RTC_ADAY0) Field Descriptions Field Value Description ADAY[7:0] Days alarm [7:0] TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 59: Rtc Days[14:8] Alarm (Rtc_Aday1) Register

    Days alarm 0000 to 7FFF coded in hexadecimal format. If 32,767 days are set to ADAY[14:0, ] then ADAY[14:0] will become 15'b111_1111_1111_1111. SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 60: Clock Control (Clkc_Cnt) Register

    1/1024 for 32 Hz 1011 1/2048 for 16 Hz 1100- 1/4096 for 8 Hz 1111 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem SPRUFJ0A – May 2009 – Revised March 2010 (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 61: Sequencer Loop Counter Value (Seq_Loop) Register

    Table 41. Sequencer Loop Counter Value (SEQ_LOOP) Field Descriptions Field Value Description LOOP Sequencer loop counter value SPRUFJ0A – May 2009 – Revised March 2010 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem (PRTCSS) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...

  • Page 62: Appendix A Revision History

    Changed subsection title. Section 3.3.2.2 Changed subsection title. Section 3.3.2.3 Changed subsection title. Figure 16 Changed Read and Read/Write values in table. Revision History SPRUFJ0A – May 2009 – Revised March 2010 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated...
  • Page 63 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

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