Texas Instruments TMS320DM36X User Manual
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Texas Instruments TMS320DM36X User Manual

Texas Instruments TMS320DM36X User Manual

Digital media system-on-chip (dmsoc), ethernet media access controller (emac)
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TMS320DM36x Digital Media System-on-Chip
(DMSoC)
Ethernet Media Access Controller (EMAC)
User's Guide
Literature Number: SPRUFI5B
March 2009 – Revised December 2010

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Summary of Contents for Texas Instruments TMS320DM36X

  • Page 1 TMS320DM36x Digital Media System-on-Chip (DMSoC) Ethernet Media Access Controller (EMAC) User's Guide Literature Number: SPRUFI5B March 2009 – Revised December 2010...
  • Page 2 SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback © 2009–2010, Texas Instruments Incorporated...

  • Page 3: Table Of Contents

    EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX) 3.14 EMAC Control Module Transmit Interrupts per Millisecond Register (CMTXINTMAX) MDIO Registers SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback © 2009–2010, Texas Instruments Incorporated Table of Contents...
  • Page 4 MAC Status Register (MACSTATUS) 5.31 Emulation Control Register (EMCONTROL) 5.32 FIFO Control Register (FIFOCONTROL) 5.33 MAC Configuration Register (MACCONFIG) 5.34 Soft Reset Register (SOFTRESET) Contents SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 5 Transmit Channel 0-7 Completion Pointer Register (TXnCP) 5.49 Receive Channel 0-7 Completion Pointer Register (RXnCP) 5.50 Network Statistics Registers Appendix A Glossary Appendix B Revision History SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback © 2009–2010, Texas Instruments Incorporated Contents...
  • Page 6 Receive Control Register (RXCONTROL) Receive Teardown Register (RXTEARDOWN) Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) List of Figures List of Figures © 2009–2010, Texas Instruments Incorporated www.ti.com SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback...
  • Page 7 Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Transmit Channel n Completion Pointer Register (TXnCP) Receive Channel n Completion Pointer Register (RXnCP) Statistics Register SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback © 2009–2010, Texas Instruments Incorporated List of Figures...
  • Page 8 Receive Teardown Register (RXTEARDOWN) Field Descriptions Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions List of Tables List of Tables SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 9 Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions Physical Layer Definitions Document Revision History SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback © 2009–2010, Texas Instruments Incorporated List of Tables...

  • Page 10: Preface

    (PHY) device Management Data Input/Output (MDIO) module integrated in the TMS320DM36x Digital Media System-on-Chip (DMSoC). Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and the registers description for each module.
  • Page 11 SPRUFH5 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Multimedia Card (MMC)/Secure Digital (SD) Card Controller Users Guide This document describes the multimedia card (MMC)/secure digital (SD) card controller in the TMS320DM36x Digital Media System-on-Chip (DMSoC). SPRUFH6 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Pulse-Width Modulator (PWM) Users Guide This document describes the pulse-width modulator (PWM) peripheral in the TMS320DM36x Digital Media System-on-Chip (DMSoC).
  • Page 12 TMS320DM36x Digital Media System-on-Chip (DMSoC). SPRUFI8 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Key Scan User's Guide This document describes the key scan peripheral in the TMS320DM36x Digital Media System-on-Chip (DMSoC). SPRUFI9 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Voice Codec User's Guide This document describes the voice codec peripheral in the TMS320DM36x Digital Media System-on-Chip (DMSoC).

  • Page 13: Introduction

    No-chain mode truncates frame to first buffer for network analysis applications SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback SPRUFI5B – March 2009 – Revised December 2010 Data Input/Output (MDIO) Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated User's Guide (MDIO)

  • Page 14: Functional Block Diagram

    Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Configuration bus DMA memory transfer controller Peripheral bus EMAC control module EMAC module MDIO module MII bus SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com MDIO bus Submit Documentation Feedback...

  • Page 15: Industry Standard(S) Compliance Statement

    EMAC_TX_CLK and EMAC_RX_CLK, respectively. SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Section 2.17.4 for details of interrupt multiplex logic of the EMAC control Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture (MDIO)

  • Page 16: Memory Map

    EMAC_TX_EN EMAC_COL EMAC_CRS Physical layer EMAC_RX_CLK device EMAC_RXD(3-0) (PHY) EMAC_RX_DV MRXER MDCLK MDIO SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Table 1. For more 2.5 MHz, 25 MHz Transformer RJ-45 Submit Documentation Feedback...

  • Page 17: Pin Multiplexing

    TMS320DM365 Digital Media System-on-Chip (DMSoiC) ARM Subsystem Users Guide (SPRUFG5). SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture (MDIO)

  • Page 18: Ethernet Protocol Overview

    60 to (RXMAXLEN - 4) bytes of the packet data. Note that this 4-byte field may or may not be included as part of the packet data, depending on how the EMAC is configured. SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com 46−1500 Data...

  • Page 19: Programming Interface

    Submit Documentation Feedback Table Figure 4. Basic Descriptor Format Bit Fields 16 15 Next Descriptor Pointer Buffer Pointer Buffer Offset Flags Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture Figure Buffer Length Packet Length (MDIO)

  • Page 20: Typical Descriptor Linked List

    1514 pNext pBuffer −−− −−− pNext pBuffer −−− pNext (NULL) pBuffer 1514 1514 © 2009–2010, Texas Instruments Incorporated www.ti.com Section 2.6.4 Section 2.6.5. Packet A 60 bytes Packet B Fragment 1 512 bytes Packet B Fragment 2 502 bytes...
  • Page 21 This process applies when adding packets to a transmit list, and empty buffers to a receive list. SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture Section 2.6.1. The lists...
  • Page 22 EMAC interrupt, since the interrupt and its acknowledgment are tied directly to the actual buffer descriptors processing. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Section 2.6.2. SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Section 2.6.1, using the linked list Submit Documentation Feedback...

  • Page 23: Transmit Buffer Descriptor Format

    /* Pointer to data buffer /* Buffer Offset(MSW) and Length(LSW) /* Packet Flags(MSW) and Length(LSW) 0x80000000u 0x40000000u 0x20000000u 0x10000000u 0x08000000u 0x04000000u Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture shows the transmit buffer Buffer Length Reserved (MDIO)
  • Page 24 EOP flag. This bit is set by the software application and is not altered by the EMAC. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 25 CRC bytes, as they are part of the valid packet data. Note that this flag is valid on SOP descriptors only. SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture (MDIO)

  • Page 26: Receive Buffer Descriptor Format

    Figure 7. Receive Buffer Descriptor Format Next Descriptor Pointer Buffer Pointer 16 15 TDOWNCMPLT OVERRUN CODEERROR Packet Length SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com shows the receive buffer Buffer Length PASSCRC JABBER OVERSIZE ALIGNERROR CRCERROR...
  • Page 27 /* Buffer Offset(MSW) and Length(LSW) /* Packet Flags(MSW) and Length(LSW) 0x80000000u 0x40000000u 0x20000000u 0x10000000u 0x08000000u 0x04000000u 0x02000000u 0x01000000u 0x00800000u 0x00400000u 0x00200000u 0x00100000u 0x00080000u 0x00040000u 0x00020000u 0x00010000u Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture (MDIO)
  • Page 28 No additional queue processing is performed. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 29 RXMBPENABLE. Although the packet is a valid Ethernet data packet, it was only received because the EMAC is in promiscuous mode. SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture (MDIO)

  • Page 30: Emac Control Module

    8) are to interface the EMAC and MDIO modules Arbiter and bus switches 8K byte descriptor memory Configuration registers Interrupt control and pacing logic SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com 4 interrupts to ARM Submit Documentation Feedback...
  • Page 31 1h to signal the end of the receive interrupt processing. SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Section Section 2.7.4. The eight individual receive Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture 2.7.4. The eight individual (MDIO)
  • Page 32 1 ms going to the CPU. Similarly, the number of receive interrupt pulses to the CPU is also separately controlled. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 33: Mdio Module

    SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Figure 9. MDIO Module Block Diagram MDIO clock generator interface monitoring Control registers and logic Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture MDCLK MDIO MDIO polling (MDIO)
  • Page 34 The application software can use the ACK bit in USERACCESSn to determine the status of a read transaction. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 35 (USERINTMASKSET), then the bit is also set in the MDIO user command complete interrupt register (USERINTMASKED) and an interrupt is triggered on the CPU. SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture (MDIO)
  • Page 36 Synchronize operation (make sure read/write is idle) Wait for read to complete and return data read Section 2.8.2.3). Since the MDIO PHY alive status register (ALIVE) is SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Example 3 Submit Documentation Feedback...

  • Page 37: Emac Module

    Submit Documentation Feedback Clock and reset logic Receive Receive DMA engine FIFO receiver Interrupt State Statistics controller Transmit Transmit DMA engine FIFO transmitter Control registers Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture SYNC (MDIO)
  • Page 38 The clock and reset submodule generates all the EMAC clocks and resets. For more details on reset capabilities, see Section 2.15.1. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 39 The EMAC keeps track of 36 different statistics, plus keeps the status of each individual packet in its corresponding packet descriptor. SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture (MDIO)

  • Page 40: Media Independent Interface (Mii)

    MACCONTROL. The FULLDUPLEX bit in MACCONTROL configures the EMAC for collision or IEEE 802.3X flow control. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 41 If the RXBUFFERFLOWEN bit in MACCONTROL is cleared to 0 while the pause time is nonzero, then the pause time is cleared to 0 and a zero count pause frame is sent. SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture (MDIO)
  • Page 42 EMAC_TX_EN is deasserted, then 96 bit times (approximately, but not less) is measured from EMAC_CRS. 2.10.2.5 Back Off The EMAC implements the 802.3 binary exponential back-off algorithm. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 43 The MAC operates at 10 Mbps or 100 Mbps, in half-duplex or full-duplex mode, and with or without pause frame support as configured by the host. SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture (MDIO)

  • Page 44: 2.11 Packet Receive Operation

    RAM, then the packet will be transferred to the associated channel. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 45 (RXFILTERLOWTHRESH) value. Hardware QOS is enabled by the RXQOSEN bit in the receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE). SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture (MDIO)
  • Page 46 If the frame length is 1521, there are 1518 bytes transferred to memory regardless of the RXPASSCRC bit value. The last byte is the first CRC byte. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 47: Receive Frame Treatment Summary

    No control or undersized frames are transferred. Proper/oversize/jabber/fragment/undersized/code/ align/CRC data frames transferred to address match channel. No control frames are transferred. Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture (MDIO)

  • Page 48: Middle Of Frame Overrun Treatment

    OVERRUN flag is set in the SOP buffer descriptor. Note that the RXMAXLEN number of bytes cannot be reached for an overrun to occur (it would be truncated). © 2009–2010, Texas Instruments Incorporated www.ti.com SPRUFI5B – March 2009 – Revised December 2010...

  • Page 49: 2.12 Packet Transmit Operation

    FIFO; for a maximum-size packet, set the TXCELLTHRESH field to the maximum possible value of 24. SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture (MDIO)

  • Page 50: 2.14 Transfer Node Priority

    Unlike the EMAC module, the MDIO and EMAC control modules cannot be placed in reset from a register inside their memory map. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Section SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com 2.18. Submit Documentation Feedback...

  • Page 51: 2.16 Initialization

    (to control reentrancy) should be done at the chip level by manipulating the interrupt enable mask. SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Section 2.16. Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture Section 2.17.1.5. (MDIO)
  • Page 52 /* Enable all the EMAC/MDIO interrupts in the control module */ EmacControlRegs->CONTROL.C_RX_EN = 0xff; EmacControlRegs->CONTROL.C_TX_EN = 0xff; EmacControlRegs->CONTROL.C_RX_THRESH_EN = 0xff; EmacControlRegs->CONTROL.C_MISC_EN = 0xf; Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 53 MDIO software off a time-based event rather than polling. For more information on PHY control registers, see your PHY device documentation. SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture (MDIO)
  • Page 54 17. Enable the device interrupt in the EMAC control module interrupt control registers (CMRXTHRESHINTEN, CMRXINTEN, CMTXINTEN, and CMMISCINTEN). Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 55: 2.17 Interrupt Support

    (TXPENDn). The transmit interrupts are level interrupts that remain asserted until cleared by the CPU. SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Interrupt control and pacing logic Receive threshold interrupt Receive interrupt Transmit interrupt Miscellaneous interrupt Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture (MDIO)
  • Page 56 The host may process multiple packets prior to acknowledging an interrupt, or the host may acknowledge interrupts for every packet. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 57 The receive host error conditions are: • Ownership bit not set in input buffer • Zero buffer pointer SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture (MDIO)
  • Page 58 EMAC interrupts please refer to TMS320DM365 Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (SPRUFG5). Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 59: 2.18 Power Management

    SOFT and FREE bits affect the operation of the emulation suspend. SOFT SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Table 6. Emulation Control FREE Description Normal operation Emulation suspend Normal operation Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Architecture (MDIO)

  • Page 60: Emac Control Module Registers

    Receive Interrupts Per Millisecond Register Transmit Interrupts Per Millisecond Register Figure 12 EWIDENT R-2Eh EWMAJORVER Field Descriptions SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Section Section 3.1 Section 3.2 Section 3.3 Section 3.4 Section 3.5 Section 3.6...

  • Page 61: Emac Control Module Software Reset Register (Cmsoftreset)

    Submit Documentation Feedback Figure 13 Reserved Reserved Figure 14 Reserved Reserved Field Descriptions Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated EMAC Control Module Registers and described in Table SOFTRESET R/W-0 and described in Table SOFT...

  • Page 62: Emac Control Module Interrupt Control Register (Cmintctrl)

    0-7FFh Interrupt counter prescaler. The number of peripheral clock periods in 4 ms. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Figure 15 and described in Reserved INTPRESCALE R/W-0 Field Descriptions SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Table INTPACEEN R/W-0 Submit Documentation Feedback...

  • Page 63: Emac Control Module Receive Threshold Interrupt Enable Register (Cmrxthreshinten)

    Bit n = 0, channel n receive threshold interrupt (RXTHRESHPENDn) is disabled. Bit n = 1, channel n receive threshold interrupt (RXTHRESHPENDn) is enabled. Reserved Field Descriptions Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated EMAC Control Module Registers Figure 16 RXTHRESHEN R/W-0...

  • Page 64: Emac Control Module Transmit Interrupt Enable Register (Cmtxinten)

    Bit n = 1, channel n transmit interrupt (TXPENDn) is enabled. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Figure 18 Reserved Field Descriptions SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com and described in Table TXPULSEEN R/W-0 Submit Documentation Feedback...

  • Page 65: Emac Control Module Miscellaneous Interrupt Enable Register (Cmmiscinten)

    MDIO module user interrupt (USERINT) enable. MDIO module user interrupt (USERINT) is disabled. MDIO module user interrupt (USERINT) is enabled. Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated EMAC Control Module Registers Figure 19 and described in...

  • Page 66: Emac Control Module Receive Threshold Interrupt Status Register (Cmrxthreshintstat)

    Receive interrupt status. Each bit shows the status of the corresponding channel n receive interrupt. Bit n = 0, channel n receive interrupt is not pending. Bit n = 1, channel n receive interrupt is pending. © 2009–2010, Texas Instruments Incorporated www.ti.com Figure 20 RXTHRESHINTTSTAT...

  • Page 67: Emac Control Module Transmit Interrupt Status Register (Cmtxintstat)

    Bit n = 0, channel n transmit interrupt is not pending. Bit n = 1, channel n transmit interrupt is pending. Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated EMAC Control Module Registers Figure 22 and described in...

  • Page 68: Emac Control Module Miscellaneous Interrupt Status Register (Ewmiscstat)

    MDIO module user interrupt (USERINT) status. MDIO module user interrupt (USERINT) is not pending. MDIO module user interrupt (USERINT) is pending. SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Figure 23 and described in...

  • Page 69: Emac Control Module Receive Interrupts Per Millisecond Register (Cmrxintmax)

    SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Reserved Field Descriptions Reserved Field Descriptions Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated EMAC Control Module Registers Figure 24and described in RXIMAX R/W-0 Figure...

  • Page 70: Mdio Registers

    MDIO User Access Register 1 MDIO User PHY Select Register 1 Figure 26 and described in Figure 26. MDIO Version Register (VERSION) MODID R-7h © 2009–2010, Texas Instruments Incorporated www.ti.com Section Section 4.1 Section 4.2 Section 4.3 Section 4.4 Section 4.5 Section 4.6...

  • Page 71: Mdio Control Register (Control)

    Clock Divider bits. This field specifies the division ratio between the peripheral clock and the frequency of MDCLK. MDCLK is disabled when CLKDIV is set to 0. MDCLK frequency = peripheral clock frequency/(CLKDIV + 1). Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated MDIO Registers Table FAULT...

  • Page 72: Phy Acknowledge Status Register (Alive)

    ALIVE R/W1C-0 ALIVE R/W1C-0 Figure 29 and described in Figure 29. PHY Link Status Register (LINK) LINK LINK SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com and described in Table Table Submit Documentation Feedback...

  • Page 73: Mdio Link Status Change Interrupt (Unmasked) Register (Linkintraw)

    MDIO user PHY select register n (USERPHYSELn). SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Reserved Reserved Field Descriptions Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated MDIO Registers Figure 30 LINKINTRAW R/W1C-0 (MDIO)

  • Page 74: Mdio Link Status Change Interrupt (Masked) Register (Linkintmasked)

    MDIO user PHY select register n (USERPHYSELn) and the LINKINTENB bit in USERPHYSELn is set to 1. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Reserved Reserved Field Descriptions SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Figure 31 LINKINTMASKED R/W1C-0 Submit Documentation Feedback...

  • Page 75: Mdio User Command Complete Interrupt (Unmasked) Register (Userintraw)

    The previously scheduled PHY read or write command using MDIO user access register n (USERACCESSn) has completed. SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Table Reserved Reserved Field Descriptions Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated MDIO Registers USERINTRAW R/W1C-0 (MDIO)

  • Page 76: Mdio User Command Complete Interrupt (Masked) Register (Userintmasked)

    No MDIO user command complete event. The previously scheduled PHY read or write command using MDIO user access register n (USERACCESSn) has completed and the corresponding bit in USERINTMASKSET is set to 1. © 2009–2010, Texas Instruments Incorporated www.ti.com USERINTMASKED R/W1C-0 SPRUFI5B –...

  • Page 77: Mdio User Command Complete Interrupt Mask Set Register (Userintmaskset)

    MDIO user command complete interrupts for the MDIO user access register n (USERACCESSn) are disabled. MDIO user command complete interrupts for the MDIO user access register n (USERACCESSn) are enabled. Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated MDIO Registers USERINTMASKSET R/W1S-0 (MDIO)

  • Page 78: Mdio User Command Complete Interrupt Mask Clear Register (Userintmaskclear)

    MDIO user command complete interrupts for the MDIO user access register n (USERACCESSn) are enabled. MDIO user command complete interrupts for the MDIO user access register n (USERACCESSn) are disabled. © 2009–2010, Texas Instruments Incorporated www.ti.com USERINTMASKCLEAR R/W1C-0 SPRUFI5B – March 2009 – Revised December 2010...

  • Page 79: Mdio User Access Register 0 (Useraccess0)

    User data bits. These bits specify the data value read from or to be written to the specified PHY register. SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Figure 36 REGADR R/W-0 DATA R/W-0 Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated MDIO Registers and described in Table PHYADR R/W-0 (MDIO)

  • Page 80: Mdio User Phy Select Register 0 (Userphysel0)

    PHY address whose link status is to be monitored. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Reserved LINKSEL LINKINTENB Rsvd R/W-0 R/W-0 SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Figure 37 and described in PHYADRMON R/W-0 Submit Documentation Feedback...

  • Page 81: Mdio User Access Register 1 (Useraccess1)

    User data bits. These bits specify the data value read from or to be written to the specified PHY register. SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Figure 38 REGADR R/W-0 DATA R/W-0 Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated MDIO Registers and described in Table PHYADR R/W-0 (MDIO)

  • Page 82: Mdio User Phy Select Register 1 (Userphysel1)

    PHY address whose link status is to be monitored. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Reserved LINKSEL LINKINTENB Rsvd R/W-0 R/W-0 SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Figure 39 and described in PHYADRMON R/W-0 Submit Documentation Feedback...

  • Page 83: Ethernet Media Access Controller (Emac) Registers

    Receive Channel 5 Free Buffer Count Register Receive Channel 6 Free Buffer Count Register Receive Channel 7 Free Buffer Count Register MAC Control Register Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Section Section 5.1 Section 5.2 Section 5.3 Section 5.4...
  • Page 84 Receive Channel 3 Completion Pointer Register Receive Channel 4 Completion Pointer Register Receive Channel 5 Completion Pointer Register Receive Channel 6 Completion Pointer Register SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Section Section 5.30 Section 5.31 Section 5.32...
  • Page 85 Receive FIFO or DMA Start of Frame Overruns Register Receive FIFO or DMA Middle of Frame Overruns Register Receive DMA Overruns Register Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Section Section 5.49 Section 5.50.1 Section 5.50.2 Section 5.50.3...

  • Page 86: Transmit Identification And Version Register (Txidver)

    Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) TXIDENT R-0Ch Figure 41 and described in Reserved Reserved SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Figure 40 and described in TXMINORVER R-0Ch Table TXEN R/W-0...

  • Page 87: Transmit Teardown Register (Txteardown)

    SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC) Registers Figure 42 Reserved Reserved Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated and described in Table TXTDNCH R/W-0 (MDIO)

  • Page 88: Receive Identification And Version Register (Rxidver)

    RXMAJORVER.RXMINORVER. Current receive minor version value. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) RXIDENT R-0Ch SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Figure 43 and described in RXMINORVER R-0Ch Submit Documentation Feedback...

  • Page 89: Receive Control Register (Rxcontrol)

    Submit Documentation Feedback Ethernet Media Access Controller (EMAC) Registers Figure 44 and described in Reserved Reserved Figure 45 Reserved Reserved Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Table RXEN R/W-0 and described in Table RXTDNCH R/W-0 (MDIO)

  • Page 90: Transmit Interrupt Status (Unmasked) Register (Txintstatraw)

    TX0PEND raw interrupt read (before mask) Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Reserved Reserved TX4PEND TX3PEND TX2PEND SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Figure 46 TX1PEND TX0PEND Submit Documentation Feedback...

  • Page 91: Transmit Interrupt Status (Masked) Register (Txintstatmasked)

    TX0PEND masked interrupt read SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC) Registers Reserved Reserved TX4PEND TX3PEND TX2PEND Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Figure 47 TX1PEND TX0PEND (MDIO)

  • Page 92: Transmit Interrupt Mask Set Register (Txintmaskset)

    Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Reserved Reserved TX4MASK TX3MASK TX2MASK R/W1S-0 R/W1S-0 R/W1S-0 SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Figure 48 and described in TX1MASK TX0MASK R/W1S-0 R/W1S-0 Submit Documentation Feedback...

  • Page 93: Transmit Interrupt Mask Clear Register (Txintmaskclear)

    SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC) Registers Reserved Reserved TX4MASK TX3MASK TX2MASK R/W1C-0 R/W1C-0 R/W1C-0 Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Figure 49 and described in TX1MASK TX0MASK R/W1C-0 R/W1C-0 (MDIO)

  • Page 94: Mac Input Vector Register (Macinvector)

    Receive threshold channels 0-7 interrupt pending (RXTHRESHPENDn) status bit. Bit 8 is receive channel 0. Receive channels 0-7 interrupt pending (RXPENDn) status bit. Bit 0 is receive channel 0. Reserved Reserved © 2009–2010, Texas Instruments Incorporated www.ti.com and described in Table TXPEND...

  • Page 95: Receive Interrupt Status (Unmasked) Register (Rxintstatraw)

    RX0PEND raw interrupt read (before mask) SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC) Registers Reserved Reserved RX4PEND RX3PEND RX2PEND Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Figure 52 RX1PEND RX0PEND (MDIO)

  • Page 96: Receive Interrupt Status (Masked) Register (Rxintstatmasked)

    RX1PEND masked interrupt read RX0PEND RX0PEND masked interrupt read Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Reserved Reserved RX4PEND RX3PEND RX2PEND SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Figure 53 RX1PEND RX0PEND Submit Documentation Feedback...

  • Page 97: Receive Interrupt Mask Set Register (Rxintmaskset)

    SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC) Registers Reserved Reserved RX4MASK RX3MASK RX2MASK R/W1S-0 R/W1S-0 R/W1S-0 Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Figure 54 and described in RX1MASK RX0MASK R/W1S-0 R/W1S-0 (MDIO)

  • Page 98: Receive Interrupt Mask Clear Register (Rxintmaskclear)

    Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Reserved Reserved RX4MASK RX3MASK RX2MASK R/W1C-0 R/W1C-0 R/W1C-0 SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Figure 55 and described in RX1MASK RX0MASK R/W1C-0 R/W1C-0 Submit Documentation Feedback...

  • Page 99: Mac Interrupt Status (Unmasked) Register (Macintstatraw)

    SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC) Registers Reserved Reserved Reserved Reserved Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Figure 56 HOSTPEND STATPEND Figure 57 HOSTPEND STATPEND (MDIO)

  • Page 100: Mac Interrupt Mask Set Register (Macintmaskset)

    Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Reserved Reserved Reserved Reserved SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Figure 58 and described in HOSTMASK STATMASK R/W1S-0 R/W1S-0...

  • Page 101: Receive Multicast/Broadcast/Promiscuous Channel Enable Register (Rxmbpenable)

    SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC) Registers Table RXNOCHAIN R/W-0 Reserved Reserved Reserved Field Descriptions Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Reserved RXCMFEN R/W-0 RXPROMCH R/W-0 RXBROADCH R/W-0 RXMULTCH R/W-0 (MDIO)
  • Page 102 Multicast frames are copied to the channel selected by RXMULTCH bits. Reserved Reserved Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Field Descriptions (continued) SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 103 Select channel 7 to receive multicast frames SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC) Registers Field Descriptions (continued) Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated (MDIO)

  • Page 104: Receive Unicast Enable Set Register (Rxunicastset)

    Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Reserved Reserved RXCH4EN RXCH3EN RXCH2EN R/W1S-0 R/W1S-0 R/W1S-0 SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Figure 61 and described in RXCH1EN RXCH0EN R/W1S-0 R/W1S-0 Submit Documentation Feedback...

  • Page 105: Receive Unicast Clear Register (Rxunicastclear)

    SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC) Registers Reserved Reserved RXCH4EN RXCH3EN RXCH2EN R/W1C-0 R/W1C-0 R/W1C-0 Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Figure 62 and described in RXCH1EN RXCH0EN R/W1C-0 R/W1C-0 (MDIO)

  • Page 106: Receive Maximum Length Register (Rxmaxlen)

    15 bytes of the buffer are to be ignored by the EMAC and that valid buffer data starts on byte 16 of the buffer. This value is used for all channels. © 2009–2010, Texas Instruments Incorporated www.ti.com...

  • Page 107: Receive Filter Low Priority Frame Threshold Register (Rxfilterlowthresh)

    Reserved Receive flow threshold. These bits contain the threshold value for issuing flow control on incoming frames for channel n (when enabled). Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Figure 65 RXFILTERTHRESH R/W-0 Figure 66...

  • Page 108: Receive Channel 0-7 Free Buffer Count Register (Rxnfreebuffer)

    Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Reserved RXnFREEBUF WI-0 SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Figure 67 Submit Documentation Feedback...

  • Page 109: Mac Control Register (Maccontrol)

    Transmit pacing is enabled. MII enable bit. MII RX and TX are held in reset. MII RX and TX are enabled for receive and transmit. Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated and described in Table Rsvd TXPTYPE...
  • Page 110 FULLDUPLEX bit setting. The loopback bit should be changed only when MII bit is deasserted. Loopback mode is disabled. Loopback mode is enabled. Full-duplex mode. Half-duplex mode is enabled. Full-duplex mode is enabled. SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 111: Mac Status Register (Macstatus)

    SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC) Registers Figure 69 and described in TXERRCODE Reserved RXQOSACT Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Table Rsvd TXERRCH RXERRCH RXFLOWACT TXFLOWACT (MDIO)
  • Page 112 Any transmission in progress when this bit is asserted will complete. Transmit flow control is inactive. Transmit flow control is active. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 113: Emulation Control Register (Emcontrol)

    FIFO. This value must be greater than or equal to 2 and less than or equal to 24 (2 ≥ TXCELLTHRESH ≤ 24). Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated and described in Table...

  • Page 114: Mac Configuration Register (Macconfig)

    A software reset has occurred. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Figure 72 Figure 73 and described in Figure 73. Soft Reset Register (SOFTRESET) Reserved Reserved © 2009–2010, Texas Instruments Incorporated www.ti.com and described in Table RXCELLDEPTH R-44h MACCFIG R-3h Table...

  • Page 115: Mac Source Address Low Bytes Register (Macsrcaddrlo)

    MAC source address bits 47-40 (byte 5) SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC) Registers Reserved Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Figure 74 and described MACSRCADDR1 R/W-0 Figure 75...

  • Page 116: Mac Hash Address Register 1 (Machash1)

    Most-significant 32 bits of the hash table corresponding to hash values 32 to 63. If a hash table bit is set, then a group address that hashes to that bit index is accepted. SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com and described in...

  • Page 117: Back Off Test Register (Bofftest)

    SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC) Registers Figure 78 and described in TXBACKOFF Reserved Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Table RNDNUM Figure 79 and described in PACEVAL (MDIO)

  • Page 118: Receive Pause Timer Register (Rxpause)

    Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Figure 80 Reserved PAUSETIMER Figure 81 Reserved PAUSETIMER SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com and described in Table and described in Table Submit Documentation Feedback...

  • Page 119: Mac Address Low Bytes Register (Macaddrlo)

    MAC address bits 15-8 (byte 1) SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC) Registers VALID R/W-x Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Figure 82 MATCHFILT CHANNEL R/W-x R/W-x MACADDR1...

  • Page 120: Mac Address High Bytes Register (Macaddrhi)

    Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Figure 84 and described in Figure 84. MAC Index Register (MACINDEX) Reserved Reserved © 2009–2010, Texas Instruments Incorporated www.ti.com Figure 83 and described in Table MACADDR3 R/W-0 MACADDR5...

  • Page 121: Transmit Channel 0-7 Dma Head Descriptor Pointer Register (Txnhdp)

    Writing to these locations when they are nonzero is an error (except at reset). Host software must initialize these locations to 0 on reset. Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated Figure 85 Figure 86...

  • Page 122: Transmit Channel 0-7 Completion Pointer Register (Txncp)

    Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) TXnCP R/W-x TXnCP R/W-x RXnCP R/W-x RXnCP R/W-x SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Figure 87 and described in Figure 88 and described in Submit Documentation Feedback...

  • Page 123: 5.50 Network Statistics Registers

    SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC) Registers Figure 89) are write-to-decrement. The value written is Figure 89. Statistics Register COUNT R/WD-0 COUNT R/WD-0 Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated (MDIO)
  • Page 124 CRC errors. Overruns have no effect on this statistic. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Section 2.6.5 for definitions Submit Documentation Feedback...
  • Page 125 • Receive jabbers • Receive overruns • Receive filtered frames SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC) Registers Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated (MDIO)
  • Page 126 Was of any length • Had no late or excessive collisions, no carrier loss, and no underrun Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 127 Experienced 2 to 15 collisions before being successfully transmitted. None of the collisions were late. SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC) Registers Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated (MDIO)
  • Page 128 Any data or MAC control frame that was destined for any unicast, broadcast, or multicast address • Did not experience late collisions, excessive collisions, underrun, or carrier sense error Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 129 CRC/alignment/code errors, underruns, and overruns do not affect frame recording in this statistic. SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Ethernet Media Access Controller (EMAC) Registers Ethernet Media Access Controller (EMAC)/Management Data Input/Output © 2009–2010, Texas Instruments Incorporated (MDIO)
  • Page 130 (zero head descriptor pointer at the start or during the middle of the frame reception). CRC errors, alignment errors, and code errors have no effect on this statistic. Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 131: Appendix A Glossary

    Descriptors are used by the EMAC and application to describe the memory buffers that hold Ethernet data. Device — In this document, device refers to the TMS320DM36x processor. Ethernet MAC Address (MAC Address)— A unique 6-byte address that identifies an Ethernet device on the network.

  • Page 132: Physical Layer Definitions

    Port— Ethernet device. Promiscuous Mode— EMAC receives frames that do not match its address. Glossary Table 87. Physical Layer Definitions SPRUFI5B – March 2009 – Revised December 2010 © 2009–2010, Texas Instruments Incorporated www.ti.com Table Submit Documentation Feedback...

  • Page 133: Appendix B Revision History

    Reference Additions/Modifications/Deletions Section 1.3 Changed fourth paragraph. SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback Table 88. Document Revision History © 2009–2010, Texas Instruments Incorporated Revision History...

  • Page 134: Important Notice

    Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

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