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Texas Instruments TMS470R1x Reference Manual

Texas Instruments TMS470R1x Reference Manual

Multi-buffer serial peripheral interface
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TMS470R1x Multi-Buffer Serial
Peripheral Interface (MibSPI)
Reference Guide
Literature Number: SPNU217B
October 2003

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Summary of Contents for Texas Instruments TMS470R1x

  • Page 1 TMS470R1x Multi-Buffer Serial Peripheral Interface (MibSPI) Reference Guide Literature Number: SPNU217B October 2003...
  • Page 3 REVISION HISTORY REVISION DATE NOTES 10/03 Register formats updated, Pages 30-101 9/02 Converted to stand-alone book 9/02 Initial version...
  • Page 4 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products...

  • Page 5: Table Of Contents

    Contents Overview ..............2 MibSPI Operation Modes .
  • Page 6 Contents MibSPI Control Register 1 (SPICTRL1) ........39 MibSPI Control Register 2 (SPICTRL2) .
  • Page 7 Figures MibSPI Module Block Diagram..........4 MibSPI Three-Pin Option .
  • Page 8 Tables MibSPI Internal Registers Mode ..........5 Clocking Modes .
  • Page 9 Chapter Multi-Buffer Serial Peripheral Interface (MibSPI) This reference guide provides the specifications for a 16-bit configurable synchronous multi-buffer serial peripheral interface (MibSPI). The MibSPI is, in effect, a programmable-length shift register used for high speed communication between external peripherals or other microcontrollers. Its multi-buffer allows multiple transmissions with different peripherals without any CPU action.

  • Page 10: Overview

    Overview Overview The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (one to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The MibSPI is normally used for communication between the microcontroller and external peripherals or another microcontroller.

  • Page 11: Mibspi Operation Modes

    MibSPI Operation Modes MibSPI Operation Modes The MibSPI operates in master or slave mode. The MASTER bit (SPICTRL2.3) selects the configuration of the SPISIMO and SPISOMI pins and the CLKMOD bit (SPICTRL2.5) determines whether an internal or external clock source will be used. The slave chip select (SPISCS[7:0]) pins are used when communicating with multiple slave devices.

  • Page 12: Mibspi Module Block Diagram

    MibSPI Operation Modes Figure 1. MibSPI Module Block Diagram Expansion bus controller External DMAreq Int0/Int1 event MIBspi Multi-buffer RAM Ctrl access control unit regs Event MibSPI mgmt interface Ctrl Stat Tick including buffer field field buffer count multi-buffer RAM and Buffer sequencer array...

  • Page 13: Mibspi Internal Registers

    MibSPI Operation Modes MibSPI Internal Registers A general representation of the MibSPI internal registers is shown in Table 1. The page column provides a cross reference to additional information on the individual registers. For more information regarding individual bytes, see Table 3, on page 30.
  • Page 14 MibSPI Operation Modes †‡ Table 1. MibSPI Internal Registers Mode (Continued) Offset † Address Mnemonic Name Description Page In CS decoded mode only: sets high low/ 048h SPICTRL6 Control Register 6 active CS signals 04Ch SPICTRL7 Control Register 7 Configuration of 2nd data word format 050h SPICTRL8 Control Register 8...

  • Page 15: Mibspi Operation; Three-Pin Option

    MibSPI Operation Modes †‡ Table 1. MibSPI Internal Registers Mode (Continued) Offset † Address Mnemonic Name Description Page 0D8h... Reserved Reserved 0FFh base1 + CTRL+TX Multi-buffer RAM Read/ 000h... Transmit and control RAM buffers Write Addresses 1FFh 200h STAT+RX Multi-buffer Read-only Receive and status RAM 3FFh buffers...

  • Page 16: Mibspi Operation; Four-Pin Option

    MibSPI Operation Modes SPIDAT0 register. When the selected number of bits has been transmitted, the data is transferred to the SPIBUF register for the CPU to read. Data is stored right-justified in SPIBUF. When the specified number of bits has been shifted through the SPIDAT0 register, the following events occur: The RXINTFLAG bit (SPICTRL3.0) is set to 1 The SPIDAT0 register contents transfer to the SPIBUF register...

  • Page 17: Four-Pin Option With Spiena

    MibSPI Operation Modes Figure 3. MibSPI Four-Pin Option with SPISCS Master Slave MibSPI four pin option (1) (Master = 1 ; CLKMOD = 1) (Master = 0 ; CLKMOD = 0) SPISIMO SPISIMO SPISOMI SPISOMI SPIDAT1 SPIDAT0 SPICLK SPICLK SPISCS SPISCS Write to SPIDAT1...

  • Page 18: Mibspi Operation; Five-Pin Option (Hardware Handshaking)

    MibSPI Operation Modes SPIENA pin will allow the master SPI to drive the clock pulse stream; otherwise, the master will hold the clock signal. To use the SPIENA as a WAIT signal pin, the slave SPIENA pin must be configured as functional (SPIPC6.0 = 1). If the SPIENA pin is in high-z mode (ENABLE_HIGHZ = 1), the slave will put SPIENA into the high-impedance once it receives a new character.

  • Page 19: Mibspi Five-Pin Option With Spiena And Spiscs

    MibSPI Operation Modes new data is written to the slave shift register (SPIDAT0) and the slave has been selected by the master (SPISCS is low). If the SPIENA pin is in push-pull mode (ENABLE_HIGHZ = 0), the slave will drive SPIENA high only if there is new data in the buffer register and the slave is selected by the master (SPISCS is low).

  • Page 20: Data Format

    MibSPI Operation Modes Data Format 2.5.1 Compatibility Mode with TMS470 SPI In compatibility mode, the data formats for the three-, four- and five-pin options are identical. CHARLEN[4:0] (SPICTRL1.4-0) specifies the number of bits (one to 16) in the data word. The CHARLEN[4:0] value directs the state control logic to count the number of bits received or transmitted to determine when a complete word is processed.
  • Page 21 MibSPI Operation Modes Data word format 0 is identical to the data word format available in the standard SPI. Data formats 1, 2 and 3 can be configured through new control registers described in Section 7.19. Each MibSPI data format includes the standard SPI data format with enhanced features: For each of the four data word formats, the shift direction can be configured individually.

  • Page 22: Clocking Modes

    MibSPI Operation Modes Clocking Modes There are four clock modes in which SPICLK may operate, depending on the choice of the phase (delay/no delay) and the polarity (rising edge/falling edge) of the clock. When operating with PHASE active, the MibSPI makes the first bit of data available after the SPIDAT0 register is written and before the first edge of SPICLK.

  • Page 23: Clock Mode With Polarity = 0 And Phase = 0

    MibSPI Operation Modes Figure 6. Clock Mode with POLARITY = 0 and PHASE = 0 Clock polarity = 0, Clock phase = 0 Write SPIDAT SPICLK SPISIMO SPISOMI Sample in reception Clock phase = 0 (SPICLK without delay) - Data is output on the rising edge of SPICLK - Input data is latched on the falling edge of SPICLK - A write to the SPIDAT register starts SPICLK Figure 7.

  • Page 24: Clock Mode With Polarity = 1 And Phase = 0

    MibSPI Operation Modes Figure 8. Clock Mode with POLARITY = 1 and PHASE = 0 Clock polarity = 1, Clock phase = 0 Write SPIDAT SPICLK SPISIMO SPISOMI Sample in reception Clock phase = 0 (SPICLK without delay) - Data is output on the falling edge of SPICLK - Input data is latched on the rising edge of SPICLK - A write to the SPIDAT register starts SPICLK Figure 9.

  • Page 25: Data Transfer Example

    MibSPI Operation Modes Data Transfer Example The following timing diagram illustrates an MibSPI data transfer between two devices using a character length of five bits. Figure 10. Five Bits per Character (Five-Pin Option) Master SPI Int. flag Slave SPI Int. flag SPISOMI from slave SPISIMO...

  • Page 26: Multi-Buffer Ram

    MibSPI Operation Modes Multi-buffer RAM The size of the multi-buffer RAM depends on the implementation. It is comprised of 0 to 128 buffers, where 0 buffers represents the special case of no multi-buffer RAM. Each entry in the multi-buffer RAM consists of four parts: a 16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field.The multi-buffer RAM can be partitioned into multiple transfer groups with a variable number of buffers each.

  • Page 27: Buffer Initialization

    MibSPI Operation Modes The trigger sources have to be defined individually for each implementation of MibSPI into a TMS470 derivative. External trigger sources might by a HET I/O channel or a GIO pin re-used as trigger input. The number of transfer groups must be defined individually for each MibSPI macro cell.

  • Page 28: Multi-Buffer In Slave Mode

    MibSPI Operation Modes TRIGEVT are not taken into account by the sequencer, so only the SPISCS pins could trigger a Transfer Group. The chip-select trigger operates as a level sensitive trigger. The PRST and ONESHOT field should be set to 0. If the corresponding Transfer Group is enabled, the multi-buffer reads the current buffer of the TG and writes it into SPIDAT1.

  • Page 29: Internal Loop-Back Test Mode (Master Only)

    MibSPI Operation Modes Once the transaction is finished, the MibSPI writes back the content of the shift-register into the Rx buffer and updates the status field. Note: If all the Transfer Groups are not needed, the number of SPISCS could be reduced to 3, 2 or 1 using the SPIPC6 register.

  • Page 30: Variable Chip Select Setup And Hold Timing (Master Only)

    MibSPI Operation Modes 2.13 Variable Chip Select Setup and Hold Timing (Master only) In order to support slow slave devices, a 5-bit delay counter can be configured to delay the data transmission after the chip select is activated. A second 5-bit delay counter can be configured to delay the chip select deactivation after the last data bit transfer.

  • Page 31: Lock Transmission

    MibSPI Operation Modes 2.14 Lock Transmission In order to be accessed, some slave device require, a command followed by data. In this case, the SPI transaction should not be interrupted by another group transfer. The LOCK bit within each buffer allows consecutive transfer to happen without interruption by another group transfer.

  • Page 32: Ena Signal Time-Out (Master Only)

    MibSPI Operation Modes 2.17 ENA Signal Time-out (Master only) The MibSPI in master mode is able to wait for the hardware handshake signal (ENA) coming from the addressed slave before performing the data transfer. To avoid stalling the MibSPI by a non-responsive slave device, a time-out value can be configured.

  • Page 33: General Purpose I/O

    General Purpose I/O General Purpose I/O Each of the SPI pins may be programmed via the SPI Pin Control Registers (SPIPC1, SPIPC2, SPIPC3, SPIPC4, SPIPC5, SPIPC6) to be a general- purpose I/O pin. When the MibSPI module is not used, the MibSPI pins may be programmed to be either general input or general output pins.

  • Page 34: Low Power Mode

    Low Power Mode Low Power Mode The MibSPI module can enter low-power mode two ways: a global low-power mode from the system and a local low-power mode via the POWERDOWN bit (SPICTRL2.2). The net effect on the MibSPI is the same, regardless of the source.

  • Page 35: Interrupts

    Interrupts Interrupts Compatibility Mode In compatibility mode, the MiBSPI generates interrupts to the highest priority. Vectorization is not enabled, which implies that the program should poll the register SPICTRL3 flags. To enable the interrupt in compatibility mode, the program should set the bit RXINTEN for receive interrupt or the bit OVRNINTEN for overrun interrupt.

  • Page 36: Transfer Group Interrupt Structure

    Interrupts Figure 13. Transfer Group Interrupt Structure LVL 0 Finished Suspended LVL 1 Transfer group x ENAx LVLx Vector X + 1 Bit 0 During transmission, if one of the following error occurs: BITERR, DESYNC, PARITYERR, TIMEOUT. The corresponding flag in the SPISTAT register is set.

  • Page 37: Dma Interface

    DMA Interface DMA Interface If handling the MibSPI message traffic on a character-by-character basis requires too much CPU overhead and if the particular device is equipped with the DMA controller, the MibSPI may use the DMA controller to receive or transmit data directly to or from memory.

  • Page 38: Control Registers And Ram

    Control Registers and RAM Control Registers This section describes the MibSPI control, data and pin registers The registers support 16-bit and 32- bit writes. The offset is relative to the associated peripheral select. Table 3. MibSPI Registers Offset Address† Register 0x00 SPICTRL1 Reserved...
  • Page 39 Table 3. MibSPI Registers (Continued) Offset Address† Register RCVR RXINT- RXEMP PARIT TIME 0x14 SPIBUF Reserved FLAG FULL SYNC YERR SPIBUF.15:0 0x18 SPIEMU Reserved SPIEMU.15:0 0x1C SPIPC1 Reserved SOMI SIMO ENABLE Reserved 0x20 SPIPC2 Reserved SOMI SIMO ENABLE Reserved 0x24 SPIPC3 Reserved SOMI...
  • Page 40 Table 3. MibSPI Registers (Continued) Offset Address† Register 0x2C SPIPC5 Reserved SOMI SIMO ENABLE DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT Reserved DOUT DOUT DOUT DOUT 0x30 SPIPC6 Reserved SOMI SIMO ENABLE Reserved 0x34 Reserved Reserved 0x38 Reserved Reserved 0x3C Reserved Reserved...
  • Page 41 Table 3. MibSPI Registers (Continued) Offset Address† Register 0x44 SPICTRL 5 Reserved C2TDELAY Reserved T2CDELAY T2EDELAY C2EDELAY 0x48 SPICTRL 6 Reserved Reserved SHIFT POLARI- Reserved 0x4C SPICTRL 7 Reserved WDELAYx PHASEx DIRx Reserv WAIT- PARI- PRESCALEx CHARLENx ENAx SHIFT POLARI- 0x50 SPICTRL 8 Reserved...
  • Page 42 Table 3. MibSPI Registers (Continued) Offset Address† Register INTEN INTEN INTEN INTEN INTEN INTEN INTEN INTEN INTEN INTEN INTEN INTEN INTEN INTEN INTEN INTEN 0x5C TGINTENA RDY15 RDY14 RDY15 RDY12 RDY11 RDY10 RDY9 RDY8 RDY7 RDY6 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0 INTEN...
  • Page 43 Table 3. MibSPI Registers (Continued) Offset Address† Register 0x74 LTGPEND Reserved Reserv LPEND Reserved 0x78 TG0CTRL PRST TGTD Reserved TRGEVT TRIGSRC SHOT Reserv Reserv PSTART PCURRENT 0x7C TG1CTRL PRST TGTD Reserved TRGEVT TRIGSRC SHOT Reserv Reserv PSTART PCURRENT 0xB0 TG14CTRL PRST TGTD Reserved...
  • Page 44 Table 3. MibSPI Registers (Continued) Offset Address† Register 0xB8 DMA0CTRL BUFID RXDMACH TXDMACH SHOT 0xBC DMA1CTRL BUFID RXDMACH TXDMACH SHOT ICOUNT Reserved COUNT 0xD0 DMA6CTRL BUFID RXDMACH TXDMACH SHOT ICOUNT Reserved COUNT 0xD4 DMA7CTRL BUFID RXDMACH TXDMACH SHOT ICOUNT Reserved COUNT †...

  • Page 45: Mibspi Ram

    MibSPI RAM This section describes the MibSPI control and data RAM. The RAM support 16-bit and 32-bit writes. The offset is relative to the Memory chip select affected to the MibSPI RAM. In the SCMRx register (MMC) associated with the Chip select used by the MibSPI RAM, the number of wait state (WS) should be set to: WS = 2 + (ICLK ratio).
  • Page 46 Table 4. MibSPI RAM (Continued) Offset Address† Register RXEMP PARIT TIME Reserve 0x200 Buffer 0 LCSNR FULL SYNC YERR RXDATA RXEMP PARIT TIME Reserve 0x204 Buffer 1 LCSNR FULL SYNC YERR RXDATA RXEMP PARIT TIME Reserve 0x3F8 Buffer 126 LCSNR FULL SYNC YERR...

  • Page 47: Mibspi Control Register 1 (Spictrl1)

    Control Registers and RAM MibSPI Control Register 1 (SPICTRL1) Bits 0x00 Reserved Bits WAITENA0 PARITY0 Reserved PRESCALE CHARLEN RWP-0 RWP-0 RW-0 RW-0 Legend: R = Read, W = write, P = Privilege mode U = Undefined; -n = Value after reset Bits 31:16 Reserved.
  • Page 48 Control Registers and RAM Bits 12:5 PRESCALE. Determines the bit transfer rate if the MibSPI is the network master. There are 255 data transfer rates (each a function of the interface clock) that can be selected. One data bit is shifted per SPICLK cycle. If the MibSPI is a network slave, the module receives a clock signal on the SPICLK pin from the network master.

  • Page 49: Mibspi Control Register 2 (Spictrl2)

    Control Registers and RAM MibSPI Control Register 2 (SPICTRL2) Bits 004h Reserved LOOPBACK RWP-0 Bits Reserved WDELAY0 RWP-0 Bits SHIFTDIR0 PAR POL0 CLKMOD SPIEN MASTER PWRDWN POLARITY PHASE RWP-0 RWP-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 Legend: RW = Read/Write in all modes, WP = Write in privilege mode only, U = Undefined, -n = Value after reset, x = indeterminate Bits 31:17 Reserved Bit 16...
  • Page 50 Control Registers and RAM Bits 13:8 WDELAY0. Delay in between transmissions for data format 0. Idle time that will be applied at the end of the current transmission if the bit WDEL is set in the current buffer. (See section 2.5.2) The delay to be applied is equal to: WDELAY * P + 2 * P ICLK...
  • Page 51 Control Registers and RAM Bit 4 SPIEN. SPI enable Holds the MibSPI in a reset state after a chip reset. The MibSPI is enabled only after a 1 is written to this bit. This bit must be set to 1 after all other MibSPI configuration bits have been written.

  • Page 52: Mibspi Control Register 3 (Spictrl3)

    Control Registers and RAM MibSPI Control Register 3 (SPICTRL3) Bits 0x08 Reserved Bits Reserved Bits ENABLE Reserved DMAREQEN OVRNINTEN RCVROVRN RXINTEN RXINTFLAG HIGHZ RW-0 RW-0 RW-0 RC-0 RW-0 RC-0 Legend: R = Read, W = write, C = Clear, U = Undefined; -n = Value after reset Bits 31:6 Reserved.
  • Page 53 Control Registers and RAM Bit 3 OVRNINTEN. Overrun interrupt enable. An interrupt is to be generated when the RCVR OVRN flag bit (SPICTRL3.2) is set by hardware. Otherwise, no interrupt will be generated. 0 = Overrun interrupt will not be generated 1 = Overrun interrupt will be generated Bit 2 RCVROVRN.

  • Page 54: Mibspi Shift Register 0 (Spidat0)

    Control Registers and RAM MibSPI Shift Register 0 (SPIDAT0) Bits 0x0C Reserved Bits SPIDAT0 RW-0 Legend: R = Read, W = write, U = Undefined; -n = Value after reset Note: Accessibility of SPIDAT0 in MibSPI mode The SPIDAT0 register is not accessible in MibSPI mode. It is only accessible in compatibility mode.

  • Page 55: Mibspi Shift Register 1 (Spidat1)

    Control Registers and RAM MibSPI Shift Register 1 (SPIDAT1) Note: Accessibility of SPIDAT1 in MibSPI mode The MibSPI kernel allows access to all bits in SPIDAT1 in MibSPI mode, whereas in compatibility mode only the least significant 16 bits can be writable.
  • Page 56 Control Registers and RAM Bit 25:24 DFSEL. Data word format select. DFSEL1 DFSEL0 Description Data word format 0 is selected (see section 7.19) for this buffer Data word format 1 is selected (see specification of existing TMS470SPI) for this buffer Data word format 2 is selected Data word format 3 is selected Bits 23:16...

  • Page 57: Mibspi Buffer Register (Spibuf)

    Control Registers and RAM MibSPI Buffer Register (SPIBUF) Note: Accessibility of SPIBUF, SPIEMU in MibSPI mode The SPIBUF and SPIEMU register are not accessible in normal MibSPI mode. They are only accessible in compatibility mode. Bits 014h RXEMPTY RXOVR TXFULL BITERR DESYNC PARITYERR...
  • Page 58 Control Registers and RAM Bit 29 TXFULL. Transmit data buffer full. This flag is a read-only flag. Writing into SPIDAT0 or SPIDAT1 field will automatically set the TXFULL flag. After transfer of the transmit data the TXFULL flag is cleared. 1 = Host provided new transmit data to SPIDAT0 or SPIDAT1.
  • Page 59 Control Registers and RAM Bit 25 TIMEOUT. Time-out due to non-activation of ENA signal. This flag is read/clear only flag, i.e. reading the flag will automatically clear it. 1 = An ENA signal time-out occurred. The MibSPI generates a time-out because the slave hasn’t responded in time by activating the ENA sig- nal after the chip select signal has been activated.
  • Page 60 Control Registers and RAM Bits 15:0 SPIBUF. MibSPI buffer. The data in this register is the data transferred from the shift-register (SPIDAT). Since the data is shifted into the MibSPI most significant bit first, for word lengths less than 16, the data is stored right-justified in the register. Note: MibSPI Buffer Reading the SPIBUF register clears the RCVROVRN (SPICTRL3.2), RXINTFLAG (SPICTRL3.0), RCVR OVRN IMG (SPIBUF.17), and the...

  • Page 61: Mibspi Emulation Register (Spiemu)

    Control Registers and RAM MibSPI Emulation Register (SPIEMU) Bits 0x18 Reserved Bits SPIEMU Legend: R = Read, U = Undefined; -n = Value after reset Bits 31:16 Reserved. Reads are undefined and writes have no effect Bits 15:0 SPIEMU. MibSPI emulation. MibSPI emulation is a mirror of the SPIBUF register.

  • Page 62: Mibspi Pin Control Register 1 (Spipc1)

    Control Registers and RAM 7.10 MibSPI Pin Control Register 1 (SPIPC1) Bits 0x1C Reserved Bits Reserved SCSDIR7 SCSDIR6 SCSDIR5 SCSDIR4 RW-0 RW-0 RW-0 RW-0 Bits SCSDIR3 SCSDIR2 SCSDIR1 SCSDIR0 SOMIDIR SIMOIDIR CLKDIR ENADIR RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 Legend: R = Read, C = Clear, U = Undefined;...
  • Page 63 Control Registers and RAM Bit 2 SIMODIR. SPISIMO direction. Controls the direction of the SPISIMO pin when it is used as a general- purpose I/O pin. If the SPISIMO pin is used as a MibSPI functional pin, the I/ O direction is determined by the MASTER bit (SPICTRL2.3). 0 = SPISIMO pin is an input 1 = SPISIMO pin is an output Bit 1...

  • Page 64: Mibspi Pin Control Register 2 (Spipc2)

    Control Registers and RAM 7.11 MibSPI Pin Control Register 2 (SPIPC2) Bits 0x20 Reserved Bits Reserved SCSDIN7 SCSDIN6 SCSDIN5 SCSDIN4 Bits SCSDIN3 SCSDIN2 SCSDIN1 SCSDIN0 SOMIDIN SIMODIN CLKDIN ENADIN Legend: R = Read, C = Clear, U = Undefined; -n = Value after reset Bits 31:12 Reserved.

  • Page 65: Mibspi Pin Control Register 3 (Spipc3)

    Control Registers and RAM 7.12 MibSPI Pin Control Register 3 (SPIPC3) Bits 0x24 Reserved Bits Reserved SCSDOUT7 SCSDOUT6 SCSDOUT5 SCSDOUT4 RW-0 RW-0 RW-0 RW-0 Bits SCSDOUT3 SCSDOUT2 SCSDOUT1 SCSDOUT0 SOMIDOUT SIMODOUT CLKDOUT ENADOUT RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 Legend: R = Read, W = Write, U = Undefined;...
  • Page 66 Control Registers and RAM Bit 1 CLKDOUT. SPICLK dataout write. Only active when the SPICLK pin is configured as a general-purpose I/O pin and configured as an output pin. The value of this bit indicates the value sent to the pin. 0 = Current value on SPICLK pin is logic 0.

  • Page 67: Mibspi Pin Control Register 4 (Spipc4)

    Control Registers and RAM 7.13 MibSPI Pin Control Register 4 (SPIPC4) Bits 0x28 Reserved Bits Reserved SCSDSET7 SCSDSET6 SCSDSET5 SCSDSET4 RW-0 RW-0 RW-0 RW-0 Bits SCSDSET3 SCSDSET2 SCSDSET1 SCSDSET0 SOMIDSET SIMODSET CLKDSET ENADSET RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 Legend: R = Read, W = Write, U = Undefined;...
  • Page 68 Control Registers and RAM Bit 2 SIMODSET. SPISIMO dataout set. Only active when the SPISIMO pin is configured as a general-purpose output pin. A value of one written to this bit sets the corresponding SPISIMODOUT bit (SPIPC3.2) to one. Write: 0 = Has no effect 1 = Logic 1 placed on SPISIMO pin Read:...

  • Page 69: Mibspi Pin Control Register 5 (Spipc5)

    Control Registers and RAM 7.14 MibSPI Pin Control Register 5 (SPIPC5) Bits 0x2C Reserved Bits Reserved SCSDCLR7 SCSDCLR6 SCSDCLR5 SCSDCLR4 RW-0 RW-0 RW-0 RW-0 Bits SCSDCLR3 SCSDCLR2 SCSDCLR1 SCSDCLR0 SOMIDCLR SIMODCLR CLKDCLR ENADCLR RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 Legend :R = Read, W = Write, U = Undefined;...
  • Page 70 Control Registers and RAM Bit 2 SIMODCLR. SPISIMO dataout clear. Only active when the SPISIMO pin is configured as a general-purpose output pin. A value of one written to this bit clears the corresponding SPISIMODOUT bit (SPIPC3.2) to zero. Write: 0 = Has no effect 1 = Logic 0 placed on SPISIMO pin Read:...

  • Page 71: Mibspi Pin Control Register 6 (Spipc6)

    Control Registers and RAM 7.15 MibSPI Pin Control Register 6 (SPIPC6) Bits 0x30 Reserved Bits Reserved SCSFUN7 SCSFUN6 SCSFUN5 SCSFUN4 RW-0 RW-0 RW-0 RW-0 Bits SCSFUN3 SCSFUN2 SCSFUN1 SCSFUN0 SOMIFUN SIMOFUN CLKFUN ENAFUN RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 Legend: R = Read, W = Write, U = Undefined;...
  • Page 72 Control Registers and RAM Bit 1 CLKFUN. MibSPI clock function. Determines whether the SPICLK pin is to be used as a general-purpose I/O pin, or as a MibSPI functional pin. 0 = SPICLK pin is a GPIO 1 = SPICLK pin is a MibSPI functional pin Bit 0 ENAFUN.

  • Page 73: Spi Control Register 4 (Spictrl4)

    Control Registers and RAM 7.16 SPI Control Register 4 (SPICTRL4) Bits 040h Reserved Bits Reserved MSPIENA RWP-0 Legend: R = Read in all modes, WP = Write in privilege mode only, U =Undefined, -n = Value after reset, x = indeterminate Bits 31:1 Reserved Bit 0...

  • Page 74: Spi Control Register 5 (Spictrl5)

    Control Registers and RAM 7.17 SPI Control Register 5 (SPICTRL5) Bits 044h Reserved C2TDELAY Reserved T2CDELAY RW-0 RW-0 Bits T2EDELAY C2EDELAY RW-0 RW-0 Legend: RW = Read/Write in all modes, WP = Write in privilege mode only, U = Undefined, -n = Value after reset Bit 31:29 Reserved Bits 28:24...

  • Page 75: Example: Tt2Cdelay = 4 Iclk Cycles

    Control Registers and RAM Bits 23:21 Reserved Bits 20:16 T2CDELAY. Transmit-end-to-chip-select-inactive-delay. T2CDELAY is used in master mode only. It defines a hold time for the slave device that delays the chip select deactivation by a multiple of ICLK cycles after the last bit is transferred. T2CDELAY can be configured between 1 and 32 ICLK cycles.

  • Page 76: Transmit-Data-Finished-To-Ena-Inactive-Time-Out

    Control Registers and RAM Figure 17. Transmit-data-finished-to-ENA-inactive-time-out SOMI T2EDELAY The time-out value is calculated as following: Equation 3. Transmit-data-finished-to-ENA-inactive-time-out Value T2EDELAY -------------------------------- - T2EDELAY SPIclock Example: SPIclock = 8 Mbit/s; T2EDELAY = 10h; > t =2µs; T2EDELAY The slave device has to disable the ENA signal within 2µs, otherwise the SDESYNC flag is set and an interrupt is asserted if enabled.

  • Page 77: Chip-Select-Active-To-Ena-Signal-Active-Time-Out

    Control Registers and RAM Figure 18. Chip-select-active-to-ENA-signal-active-time-out SOMI C2EDELAY The time-out value is calculated as following: Equation 4. Value Chip-select-active-to-ENA-signal-active-time-out C2EDELAY --------------------------------- C2EDELAY SPIclock Example: SPIclock = 8 Mbit/s; C2EDELAY = 30h; > t =6ms; C2EDELAY The slave device has to active the ENA signal within 6 ms after the MibSPI has activated the chip select signal (SCS), otherwise the TIMEOUT flag is set and a interrupt is asserted if enabled.

  • Page 78: Spi Control Register 6 (Spictrl6)

    Control Registers and RAM 7.18 SPI Control Register 6 (SPICTRL6) Bits 048h Reserved Bits Reserved Bits CSDEF7 CSDEF6 CSDEF5 CSDEF4 CSDEF3 CSDEF2 CSDEF1 CSDEF0 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 Legend: RW = Read/Write, U = Undefined, -n = Value after reset, x = indeterminate Bits 31:8 Reserved Bits 7:0...

  • Page 79: Spi Control Register 7 (Spictrl7) (Spictrl8, Spictrl9)

    Control Registers and RAM 7.19 SPI Control Register 7 (SPICTRL7) (SPICTRL8, SPICTRL9) The MibSPI supports 4 data format transmission. The data format specifies the number of bit, the clock speed, the phase, the polarity, and the direction of a transaction. This allows the MibSPI to communicate with different type of SPI Slave without reprogramming each time the MibSPI.
  • Page 80 Control Registers and RAM Bits 21:18 Reserved Bit 15 WAITENAx. Master waits for ENA signal from slave for data format x. WAITENA is considered in master mode only. In slave mode this bit has no meaning. WAITENA enables a flexible SPI network where slaves with ENA signal and slaves without ENA signal can be mixed.
  • Page 81 Control Registers and RAM Bits 12:5 PRESCALEx. SPI data format x prescaler. PRESCALEx can be modified in privilege mode only. PRESCALEx determines the bit transfer rate of data format x if the SPI is the network master. PRESCALEx is directly derived from ICLK. If the MibSPI is configured as slave PRESCALEx DOES NOT NEED to be configured.

  • Page 82: Spi Status Register (Spistat)

    Control Registers and RAM 7.20 SPI Status Register (SPISTAT) Bits 058h Reserved BITERRLVL DESYNCLVL PARERRLVL TIMEOUTLVL RW-0 RW-0 RW-0 RW-0 Bits Reserved BITERRENA DESYNCENA PARERRENA TIMEOUTENA RW-0 RW-0 RW-0 RW-0 Bits Reserved BITERR DESYNC PARITYERR TIMEOUT RC-0 RC-0 RC-0 RC-0 Bits LCSNR Legend: R = Read, W = Write, C = Clear, U = Undefined, -n = Value after reset, x = indeterminate...
  • Page 83 Control Registers and RAM Bits 23:20 Reserved Bit 19 BITERRENA. Enables interrupt on bit error. 1 = Enables an interrupt on a bit error (BITERR = 1). 0 = No interrupt asserted upon bit error. Bit 18 DESYNCENA. Enables interrupt on de-synchronized slave. DESYNCENA is used in master mode only.
  • Page 84 Control Registers and RAM Bit 10 DESYNC. De-synchronization of slave device. This flag is read/clear only flag, i.e. reading the flag will automatically clear it. De-synchronization monitor is active in master mode only. 1 = A slave device is de-synchronized. The master monitors the ENAble signal coming from the slave device and sets the DESYNC flag if ENA is deactivated before the last reception point or after the last bit is transmitted plus t...

  • Page 85: Transfer Group Interrupt Enable Register (Tgintena)

    Control Registers and RAM 7.21 Transfer Group Interrupt Enable Register (TGINTENA) The register TGINTENA comprises the transfer group interrupt enable flags for “transfer finished” and for “transfer suspended”. The number of implemented transfer groups is dependent on the MibSPI macro-cell. Each of the enable bits in the higher half-word and the lower half-word of TGINTENA belongs to one transfer group.

  • Page 86: Transfer Group Interrupt Level Register (Tgintlvl)

    Control Registers and RAM 7.22 Transfer Group Interrupt Level Register (TGINTLVL) The register TGINTLVL comprises the transfer group interrupt level flags for “transfer finished” event and for “transfer suspended” event. With each of the flags the corresponding interrupt can be mapped to either INT0 interrupt line or INT1 interrupt line.

  • Page 87: Transfer Group Interrupt Flag Register (Tgintflag)

    Control Registers and RAM 7.23 Transfer Group Interrupt Flag Register (TGINTFLAG) The register TGINTFLAG comprises the transfer group interrupt flags for “transfer finished” interrupts (INTFLGRDYx) and for “transfer suspended” interrupts (INTFLGSUSx). The number of implemented transfer groups is dependent on the MibSPI macro-cell. Each of the interrupt flags in the higher half-word and the lower half-word of TGINTFLAG belongs to one transfer group.
  • Page 88 Control Registers and RAM Bits 15:0 INTFLGSUSx. Transfer group interrupt flag for “transfer suspend” interrupt. These flag are read/clear register.Reading the interrupt vector registers TGINTVECT0 or TGINTVECT1 is clearing automatically the referenced interrupt flag INTFLGSUSx. 1 = A “transfer suspended” interrupt from transfer group x occurred. No matter whether the interrupt is enabled or disabled (INTENSUSx = don’t care) or whether the interrupt is mapped to line INT0 or INT1, INTFLGSUSx is set right after the transfer from transfer group x is sus-...

  • Page 89: Transfer Group Interrupt Vector Register 0 (Tgintvect0)

    Control Registers and RAM 7.24 Transfer Group Interrupt Vector Register 0 (TGINTVECT0) The register TGINTVECT0 returns a vector of the highest prior interrupt that is enabled for interrupt line INT0, no matter whether it is a “transfer finished” interrupt or a “transfer suspended” interrupt. The transfer group with the lowest number (transfer group 0) has the highest priority.

  • Page 90: Interrupt Vector For Interrupt Line Int0

    Control Registers and RAM Table 5. Interrupt Vector for Interrupt Line INT0 INTVECT0[5:1] Description 00000b no interrupt pending Pending interrupt of transfer group 0. Refer to the flag SUS- 00001b PEND to determine the interrupt type (transfer suspended, transfer finished). Pending interrupt of transfer group 1.

  • Page 91: Transfer Group Interrupt Vector Register 1 (Tgintvect1)

    Control Registers and RAM 7.25 Transfer Group Interrupt Vector Register 1 (TGINTVECT1) The register TGINTVECT1 returns a vector of the highest prior interrupt that is enabled for interrupt line INT1, no matter whether it is a “transfer finished” interrupt or a “transfer suspended” interrupt. The transfer group with the lowest number (transfer group 0) has the highest priority.

  • Page 92: Interrupt Vector For Interrupt Line Int1

    Control Registers and RAM Table 6. Interrupt Vector for Interrupt Line INT1 INTVECT1[5:1] Description 00000b no interrupt pending Pending interrupt of transfer group 0. Refer to the flag SUS- 00001b PEND to determine the interrupt type (transfer suspended, transfer finished). Pending interrupt of transfer group 1.

  • Page 93: Tick Count Register (Tickcnt)

    Control Registers and RAM 7.26 Tick Count Register (TICKCNT) One of the trigger sources for transfer groups is a MibSPI internal periodic time trigger. This time trigger is called tick counter and is basically a down- counter with a pre-load/reload value. Every time the tick counter detects an under-flow it reloads the initial value and toggles the trigger signal provided to the transfer groups.
  • Page 94 Control Registers and RAM Bit 30 RELOAD. Pre-load tick counter. RELOAD is a set-only bit, i.e. writing a “1” to it automatically reloads the tick counter with the value stored in TICKICNT. Reading RELOAD always returns a “0”. Note: When the tick counter is reloaded by the RELOAD bit, the trigger signal is not toggled.

  • Page 95: Last Transfer Group End Pointer (Ltgpend)

    Control Registers and RAM 7.27 Last Transfer Group End Pointer (LTGPEND) Bits 074h Reserved Bits Reser LPEND Reserved RW-0 Legend: R = Read, W = Write, C = Clear, U = Undefined, -n = Value after reset, x = indeterminate Bits 31:15 Reserved Bits 14:8...

  • Page 96: Mibspi Transfer Group Control Register (Tgxctrl)

    Control Registers and RAM 7.28 MibSPI Transfer Group Control Register (TGxCTRL) The number of transfer groups is scalable by design. Depending on the implementation the number of transfer groups and hence the number of transfer group control register may vary. Each transfer group can be configured via one dedicated control register.
  • Page 97 Control Registers and RAM Bits 29 PRST. Transfer group pointer reset mode. With PRST the way of resolving trigger events during an ongoing transfer from the concerned transfer group can be configured. 1 = The corresponding transfer group pointer (PCURRENT) will be reset to the start address (PSTART) when a valid trigger event occurs at the selected trigger source while a transfer from the same transfer group is ongoing.

  • Page 98: Trigger Event Types

    Control Registers and RAM Table 7. Trigger Event Types TRIGEVT[3:0] Type Description 0000b never A rising edge (0>1) at the selected trigger source (TRIG- rising 0001b SRC) initiates a transfer from the corresponding transfer edge group A falling edge (1>0) at the selected trigger source (TRIG- falling 0010b SRC) initiates a transfer from the corresponding transfer...

  • Page 99: Trigger Sources

    Control Registers and RAM Table 8. Trigger Sources TRIGSRC[3:0] Type Description 0000b disabled MibSPI external trigger source 0. Source has to be 0001b EXT0 defined individually for each Microcontroller derivative (e.g. HET I/O channel, event pin, etc.). MibSPI external trigger source 1. Source has to be 0010b EXT1 defined individually for each Microcontroller derivative...

  • Page 100: Mibspi Dma Channel Control Register (Dmaxctrl)

    Control Registers and RAM 7.29 MibSPI DMA Channel Control Register (DMAxCTRL) The number of bidirectional DMA channels (requires two physical DMA channels at the DMA controller: one for the transmit path and one for the receive path) is scalable by design. Depending on the implementation the number of DMA channels and hence the number of DMA channel control registers may vary.
  • Page 101 Control Registers and RAM Bits 23:20 RXDMACH. Receive data DMA channel Each MibSPI DMA channel can be linked to two physical DMA channels of the DMA controller. One channel for receive data and one channel for transmit data. RXDMACH[3:0] defines the number of the physical DMA channel that is connected to the receive path of the MibSPI DMA channel.
  • Page 102 Control Registers and RAM Bit 13 NOBRK. non-interleaved DMA block transfer. 1 = NOBRK ensures that ICOUNT+1 data transfers are performed from the buffer referenced by BUFID without a data transfer from any other buffer. The sequencer remains at the DMA buffer until ICOUNT+1 transfers have been processed.

  • Page 103: Multi-Buffer Ram

    Control Registers and RAM 7.30 Multi-buffer RAM The multi-buffer RAM comprises all buffers, which can be configured identically. The buffers can be partitioned into multiple transfer groups, each containing a variable number of buffers. Each of the buffers can be sub- divided into a 16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field, as displayed in Figure 19.

  • Page 104: Control Field

    Control Registers and RAM 7.30.1 Control Field Bits base1+ 000h... BUFMODE CSHOLD LOCK WDEL DFSEL CSNR 1FFh RW-0 RW-0 RW-0 RW-0 RW-x Legend: R = Read, W = Write, U = Undefined, -n = Value after reset, x = indeterminate Bits 15:13 BUFMODE Buffer sequencing mode.
  • Page 105 Control Registers and RAM When one of the “skip” modes is selected, the sequencer checks the buffer status every time it comes along. If the current buffer status (TXFULL, RXEMPTY) does not match the buffer is skipped without data transfer. When one of the “suspend”...

  • Page 106: Transmit Field

    Control Registers and RAM Bit 9:8 DFSEL. Data word format select. DFSEL1 DFSEL0 Description Data word format 0 is selected (see section 7.3 and section 7.4) for this buffer Data word format 1 is selected (see section 7.19) for this buffer Data word format 2 is selected (see section 7.19) for this buffer...

  • Page 107: Status Field

    Control Registers and RAM 7.30.3 Status Field Bits base1+ 200h... RXEMPTY RXOVR TXFULL BITERR DESYNC PARITYERR TIMEOUT Reserved 3FFh RC-0 RC-0 RC-0 RC-0 RC-0 Bits base1+ 200h... LCSNR 3FFh Legend: RC = Read with auto-clear, U = Undefined, -n = Value after reset, x = indeterminate Bit 15 RXEMPTY.
  • Page 108 Control Registers and RAM Bit 12 BITERR. Mismatch of internal transmit data and transmitted data. This flag is read/clear only flag, i.e. reading the flag will automatically clear it. It represents a copy of the BITERR flag in SPISTAT. 1 = A bit error occurred. The MibSPI samples the signal of the transmit pin (master: SIMO, slave: SOMI) at the receive point (half clock cycle after transmit point).

  • Page 109: Receive Field

    Control Registers and RAM Bit 9 TIMEOUT. Time-out due to non-activation of ENA signal. This flag is read/clear only flag, i.e. reading the flag will automatically clear it. 1 = An ENA signal time-out occurred. The MibSPI generates a time-out because the slave hasn’t responded in time by activating the ENA sig- nal after the chip select signal has been activated.

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