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Texas Instruments EMIF16 User Manual

Texas Instruments EMIF16 User Manual

External memory interface
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KeyStone Architecture
External Memory Interface (EMIF16)
User Guide
Literature Number: SPRUGZ3A
May 2011

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Summary of Contents for Texas Instruments EMIF16

  • Page 1 KeyStone Architecture External Memory Interface (EMIF16) User Guide Literature Number: SPRUGZ3A May 2011...

  • Page 2: Release History

    May 2011 ‘‘Introduction’’ In the ‘‘Features’’ section, updated the description of features not supported and added additional information about the 64MB limit. January 2011 Initial Release ø-ii KeyStone Architecture External Memory Interface (EMIF16) User Guide SPRUGZ3A—May 2011 Submit Documentation Feedback...

  • Page 3: Table Of Contents

    2.4 Configuring the EMIF16 for Asynchronous Access........
  • Page 4 4.27 NAND Flash Error Value 2 Register (NANDFEV2R) ..........4-26 Index IX-1 ø-iv KeyStone Architecture External Memory Interface (EMIF16) User Guide SPRUGZ3A—May 2011 Submit Documentation Feedback...

  • Page 5: List Of Tables

    NAND Flash Error Value 2 Register (NANDFEV2R) Description ........... . 4-26 SPRUGZ3A—May 2011 KeyStone Architecture External Memory Interface (EMIF16) User Guide ø-v...
  • Page 6 NAND Flash Error Value 2 Register (NANDFEV2R) ..............4-26 ø-vi KeyStone Architecture External Memory Interface (EMIF16) User Guide SPRUGZ3A—May 2011...

  • Page 7: Ø-Vii

    This document describes the operation of the External Memory Interface (EMIF16) module in the KeyStone DSP family (refer to the device data manual for applicability to a particular part). The EMIF16 module is accessible across all the cores and all system masters that are not cores.

  • Page 8: Related Documentation From Texas Instruments

    Forum C66x CorePac User Guide SPRUGW0 Trademarks All brand names and trademarks mentioned in this document are the property of Texas Instruments Incorporated or their respective owners, as applicable. ø-viii KeyStone Architecture External Memory Interface (EMIF16) User Guide SPRUGZ3A—May 2011...

  • Page 9: Introduction

    Chapter 1 Introduction This manual describes the External Memory Interface peripheral utilizing a 16-bit bus (EMIF16). This manual describes the purpose, features, architecture, operating modes, and registers of the EMIF16. This chapter provides the following information: "Purpose of the Peripheral" on page 1-2 1.2 "Features"...

  • Page 10: Purpose Of The Peripheral

    1.1 Purpose of the Peripheral The EMIF16 module is intended to provide a glue-less interface to a variety of asynchronous memory devices like ASRAM, NOR and NAND memory. A total of 256M bytes of any of these memories can be accessed at any given time via four chip selects with 64M byte access per chip select.

  • Page 11: Architecture

    Descriptions" on page 2-2 "Memory Organization" on page 2-3 "Supported Modes" on page 2-3 "Configuring the EMIF16 for Asynchronous Access" on page 2-3 "ASRAM/NOR Flash Interface" on page 2-4 SPRUGZ3A—May 2011 KeyStone Architecture External Memory Interface (EMIF16) User Guide Submit Documentation Feedback...

  • Page 12: Emif16 Signal Descriptions

    2.1 EMIF16 Signal Descriptions Chapter 2—Architecture www.ti.com 2.1 EMIF16 Signal Descriptions A basic block diagram of the EMIF16 asynchronous interface is shown in Figure 2-1. Table 2-1 below lists the asynchronous signals of the EMIF16 module. Figure 2-1 Basic Block diagram for EMIF16...

  • Page 13: Memory Organization

    WE Strobe Mode • Select Strobe Mode EMIF16 is clocked at CPU/6 frequency. So, for a device running at 1GHz, EMIF16 is clocked at 166.67 MHz. All references to clock/clock cycles are in terms of EMIF16 clock cycles. In WE Strobe mode, the byte enables EMIFBE[1:0] can be used as write strobes for the current active chip select space.

  • Page 14: Asram/Nor Flash Interface

    2.5 ASRAM/NOR Flash Interface Chapter 2—Architecture www.ti.com 2.5 ASRAM/NOR Flash Interface EMIF16 connection diagrams for 16-bit and 8-bit SRAM/NOR Flash connected to chip select0 are shown in Figure 2-2 & Figure 2-3 respectively. Figure 2-2 Connecting to 16-bit ASRAM (see note below)

  • Page 15: Emif16 Signal Description - Asram/Nor Flash

    EMIFCE, EMIFWE, EMIFOE, EMIFBE[1:0] are the control signals that determine the start and end of the read/write cycles. Figure 2-4 Figure 2-5 show reads and writes initiated by different control signals. SPRUGZ3A—May 2011 KeyStone Architecture External Memory Interface (EMIF16) User Guide Submit Documentation Feedback...

  • Page 16: Programmable Emif16 Parameters

    Data width - Width of the asynchronous device’s data bus (8/16-bit). The setup, strobe and hold parameters are in terms of EMIF16 clock cycles. Note that EMIF16 is clocked at CPU/6 (166.67 MHz for 1 GHz CPU frequency). The setup, strobe and hold values for reads can be calculated as follows (assume CPU=1 GHz).

  • Page 17: Switching Waveforms

    Note— asynchronous access cycle, multiple cycles will be needed to complete the single read or write request. In this case, the EMIF16 enters the setup phase directly without incurring turnaround cycles. 2: If the entire read or write access has completed and there are more Note—...

  • Page 18: Asynchronous Writes

    Address on address lines EMIFA[23:0] become invalid. – EMIFD[15:0] becomes inactive. – EMIFCE becomes inactive (if no additional read/write accesses to the same chip select space are pending). KeyStone Architecture External Memory Interface (EMIF16) User Guide SPRUGZ3A—May 2011 Submit Documentation Feedback...

  • Page 19: Select Strobe Mode

    Note— asynchronous access cycle, multiple cycles are needed to complete the single read or write request. In this case, the EMIF16 enters the setup phase directly without incurring turnaround cycles. 2: If the entire read or write access has completed and there are more Note—...

  • Page 20: Asynchronous Reads In Ss Mode

    Note— asynchronous access cycle, multiple cycles will be needed to complete the single read or write request. In this case, the EMIF16 enters the setup phase directly without incurring turnaround cycles. 2: If the entire read or write access has completed and there are more Note—...

  • Page 21: Asynchronous Writes In Ss Mode

    Note— asynchronous access cycle, multiple cycles will be needed to complete the single read or write request. In this case, the EMIF16 enters the setup phase directly without incurring turnaround cycles. If the entire read or write access has completed and there are more Note—...

  • Page 22: We Strobe Mode

    2-8), the byte enables act as write strobes. This mode is useful for combining two 8-bit devices to create a 16-bit data bus, allowing the EMIF16 to perform byte writes to two 8-bit devices which do not have byte enable inputs. In WE strobe mode, the byte enables are connected to the write strobes of the 8-bit devices.

  • Page 23: Asynchronous Writes (We Strobe Mode)

    EMIFRnW Figure 2-9 Asynchronous Reads (WE Strobe Mode) Read setup Read strobe Read hold EMIFCE EMIFBE[1:0] Byte enables EMIFA[23:0] Address EMIFD[15:0] Read data EMIFOE EMIFWE EMIFRnW SPRUGZ3A—May 2011 KeyStone Architecture External Memory Interface (EMIF16) User Guide 2-13 Submit Documentation Feedback...
  • Page 24 2.5 ASRAM/NOR Flash Interface Chapter 2—Architecture www.ti.com 2-14 KeyStone Architecture External Memory Interface (EMIF16) User Guide SPRUGZ3A—May 2011 Submit Documentation Feedback...

  • Page 25: Operating Modes

    Mode" on page 3-9 "Data Bus Parking" on page 3-9 3.10 "Interrupt Support" on page 3-9 3.11 "NOR Flash Page Mode" on page 3-10 3.12 "Reset Considerations" on page 3-10 SPRUGZ3A—May 2011 KeyStone Architecture External Memory Interface (EMIF16) User Guide Submit Documentation Feedback...

  • Page 26: Nand Flash Mode

    The following sections describe connecting to a NAND Flash device, configuring EMIF16 registers for NAND Flash mode, command set, ECC support and so on. 3.1.1 Connecting to NAND Flash Figure 3-1...

  • Page 27: Configuring Emif16 In Nand Flash Mode

    3.2 Configuring EMIF16 in NAND Flash Mode EMIF16's memory-mapped registers must be programmed to configure NAND mode. In addition to configuring the fields in the Async Config Register for the chip select under consideration, the NAND Flash Control Register (NANDFCR) also needs to be configured.

  • Page 28: Using Ale And Cle

    After a read command is issued, it takes time t for the read data to be driven on the IO pins. Since chip select is inactive during this time, EMIF16 does not support Note— NAND devices that require the chip select to be low during t Each NAND operation starts off with issuing a command cycle.

  • Page 29: Checking The Status Of Operation

    R/B# goes low and remains low while the NAND Flash programs the device with the write data from the EMIF16. Once the device is free to accept the next transaction, the R/B# signal goes high. Thus, software can use the NANDFSR to determine the status of the Flash device and determining when to submit the next transaction.
  • Page 30 8-bit values for both 8-bit and 16-bit devices. The 8-bit value is converted to 10 bits and the upper 2 bits of the 10-bit value are zeroed out by EMIF16. Typically, spare area in NAND is used to store ECC-related information. For example, after a write, for the...
  • Page 31 Write the 10-bit parity values in the NAND Flash 4-Bit ECC Load Register. 7. Dummy Read: Perform a dummy read to EMIF16 Revision Code and Status Register. This ensures sufficient time for syndrome calculation after writing the ECC values in previous step.
  • Page 32 Error value from NAND Flash Error Value 1-2 Registers can be read and corrected by XOR – ing the errored word with the error value from NAND Flash Error Value 1-2 Registers. KeyStone Architecture External Memory Interface (EMIF16) User Guide SPRUGZ3A—May 2011 Submit Documentation Feedback...

  • Page 33: Extended Wait Mode

    Async 1-4 Config Registers. Extended Wait Mode is enabled by setting the EW bit in the Async 1-4 Config Register to 1. Once EW has been set, the EMIF16 monitors the EMIFWAIT pin mapped to that chip select to determine if the device wants to extend the strobe period.

  • Page 34: Nor Flash

    End of Table 3-4 3.11 NOR Flash Page Mode EMIF16 supports Page Mode reads for NOR Flash on asynchronous memory chip selects. Page Mode can be enabled by writing a ‘1’ to the CSN_PG_MD_EN field in the Page Mode Control Register (PMCR) for chip selected in consideration. For more...

  • Page 35: Registers

    "NAND Flash Error Address 2 Register (NANDFEA2R)" on page 4-24 4.26 "NAND Flash Error Value 1 Register (NANDFEV1R)" on page 4-25 4.27 "NAND Flash Error Value 2 Register (NANDFEV2R)" on page 4-26 SPRUGZ3A—May 2011 KeyStone Architecture External Memory Interface (EMIF16) User Guide Submit Documentation Feedback...

  • Page 36: Registers Overview

    4.1 Registers Overview This section details the programmable register fields within the EMIF16’s configuration space that can be programmed to configure the EMIF16, and details on memory map and bit positions. Due to legacy considerations, CS2 will refer to chip select 0 (CE0), Note—...

  • Page 37: Revision Code And Status Register (Rcsr)

    Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. 29-16 MOD_ID 0x46 Module ID Bits 15-8 MJ_REV Major Revision MIN_REV Minor Revision End of Table 4-2 SPRUGZ3A—May 2011 KeyStone Architecture External Memory Interface (EMIF16) User Guide Submit Documentation Feedback...

  • Page 38: Async Wait Cycle Config Register (Awccr)

    0x0 – Reserved. 0x0 – Reserved. 17-16 CS2_WAIT WAIT map bits for CE0: 0x0 – WAIT[0] is used. 0x0 – WAIT[1] is used. 0x0 – Reserved. 0x0 – Reserved. KeyStone Architecture External Memory Interface (EMIF16) User Guide SPRUGZ3A—May 2011 Submit Documentation Feedback...
  • Page 39 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. MAX_EXT_WAIT 0x80 Maximum extended wait cycles. EMIF16 will wait for (MAX_EXT_WAIT + 1) x 16 cycles before an extended asynchronous cycles is terminated. End of Table 4-3 SPRUGZ3A—May 2011...

  • Page 40: Async 1 Config Register (A1Cr)

    25-20 W_STROBE 0x3F Write Strobe Duration cycles. Number of EMIF16 clock cycles for which EMIFWE is held active, minus one cycle. The reset value is 64 cycles. This field cannot be zero when EW = 1. 19-17 W_HOLD Write Strobe Hold cycles.

  • Page 41: Async 2 Config Register (A2Cr)

    Description Turn Around cycles. Number of EMIF16 clock cycles between the end of one asynchronous memory access and the start of another asynchronous memory access, minus one cycle. This delay is not incurred between a read followed by a read, or a write followed by a write to the same chip select.

  • Page 42: Interrupt Raw Register (Irr)

    Writing a 1 will clear this bit as well as the AT_MASKED bit in the Interrupt Masked register. Writing a 0 has no effect. End of Table 4-5 KeyStone Architecture External Memory Interface (EMIF16) User Guide SPRUGZ3A—May 2011 Submit Documentation Feedback...

  • Page 43: Interrupt Masked Register (Imr)

    Writing a 1 will clear this bit as well as the AT bit in the Interrupt Raw register. Writing a 0 has no effect. End of Table 4-6 SPRUGZ3A—May 2011 KeyStone Architecture External Memory Interface (EMIF16) User Guide Submit Documentation Feedback...

  • Page 44: Interrupt Mask Set Register (Imsr)

    Writing a 1 will enable the interrupt, and set this bit as well as the AT_MASK_CLR bit in the Interrupt Mask Clear register. Writing a 0 has no effect. End of Table 4-7 4-10 KeyStone Architecture External Memory Interface (EMIF16) User Guide SPRUGZ3A—May 2011 Submit Documentation Feedback...

  • Page 45: Interrupt Mask Clear Register (Imcr)

    Writing a 1 will disable the interrupt, and set this bit as well as the AT_MASK_SET bit in the Interrupt Mask Set register. Writing a 0 has no effect. End of Table 4-8 SPRUGZ3A—May 2011 KeyStone Architecture External Memory Interface (EMIF16) User Guide 4-11 Submit Documentation Feedback...

  • Page 46: Nand Flash Control Register (Nandfcr)

    Writing a 0 has no effect. Reserved Reserved. The reserved bit location is always read as 0. A value written to this field has no effect 4-12 KeyStone Architecture External Memory Interface (EMIF16) User Guide SPRUGZ3A—May 2011 Submit Documentation Feedback...
  • Page 47 Set to 1 if using NAND Flash on CE1. CS1_USE_NAND NAND Flash mode for chip select CE0. Set to 1 if using NAND Flash on CE0 End of Table 4-9 SPRUGZ3A—May 2011 KeyStone Architecture External Memory Interface (EMIF16) User Guide 4-13 Submit Documentation Feedback...

  • Page 48: Nand Flash Status Register (Nandfsr)

    These bits show the raw status of the EMIFWAIT[1:0] input. The WP1-0 bits in the Async Wait Cycle Config register have no effect on these bits. End of Table 4-10 4-14 KeyStone Architecture External Memory Interface (EMIF16) User Guide SPRUGZ3A—May 2011 Submit Documentation Feedback...

  • Page 49: Page Mode Control Register (Pmcr)

    CS5_PG_DEL 0x3F Page access delay for NOR Flash connected on CE3. Number of EMIF16 clock cycles required for the page read data to be valid, minus one cycle. This value must not be set to 0. CS5_PG_SIZE Page Size for NOR Flash connected on CE3.
  • Page 50 0x0 – 4 word page. CS2_PG_MD_EN Page Mode enable for NOR Flash connected on CE0. 0x1 – Use page mode. 0x0 – Disable page mode. End of Table 4-11 4-16 KeyStone Architecture External Memory Interface (EMIF16) User Guide SPRUGZ3A—May 2011 Submit Documentation Feedback...

  • Page 51: Nand Flash Cs2 (Ce0) 1-Bit Ecc Register (Nfecccs2R)

    For 16-bit NAND Flash, p1e, p2e, p4e and p8e are column parities. p16e to p2048e are row parities. End of Table 4-12 SPRUGZ3A—May 2011 KeyStone Architecture External Memory Interface (EMIF16) User Guide 4-17 Submit Documentation Feedback...

  • Page 52: Nand Flash Cs3 (Ce1) 1-Bit Ecc Register (Nfecccs3R)

    4BIT_ECC_LOAD 4-Bit ECC Load. This register is used to load 4-bit ECC values when performing syndrome calculation during NAND Flash reads. End of Table 4-13 4-18 KeyStone Architecture External Memory Interface (EMIF16) User Guide SPRUGZ3A—May 2011 Submit Documentation Feedback...

  • Page 53: Nand Flash 4-Bit Ecc 1 Register (Nandf4Becc1R)

    Reserved. The reserved bit location is always read as 0. A value written to this field has no effect 4BIT_ECC_VAL1 4-Bit ECC or syndrome value 1 calculated while writing or reading NAND Flash. End of Table 4-14 SPRUGZ3A—May 2011 KeyStone Architecture External Memory Interface (EMIF16) User Guide 4-19 Submit Documentation Feedback...

  • Page 54: Nand Flash 4-Bit Ecc 2 Register (Nandf4Becc2R)

    Reserved. The reserved bit location is always read as 0. A value written to this field has no effect 4BIT_ECC_VAL3 4-Bit ECC or syndrome value 3 calculated while writing or reading NAND Flash. End of Table 4-15 4-20 KeyStone Architecture External Memory Interface (EMIF16) User Guide SPRUGZ3A—May 2011 Submit Documentation Feedback...

  • Page 55: Nand Flash 4-Bit Ecc 3 Register (Nandf4Becc3R)

    Reserved. The reserved bit location is always read as 0. A value written to this field has no effect 4BIT_ECC_VAL5 4-Bit ECC or syndrome value 5 calculated while writing or reading NAND Flash. End of Table 4-16 SPRUGZ3A—May 2011 KeyStone Architecture External Memory Interface (EMIF16) User Guide 4-21 Submit Documentation Feedback...

  • Page 56: Nand Flash 4-Bit Ecc 4 Register (Nandf4Becc4R)

    Reserved. The reserved bit location is always read as 0. A value written to this field has no effect 4BIT_ECC_VAL7 4-Bit ECC or syndrome value 7 calculated while writing or reading NAND Flash. End of Table 4-17 4-22 KeyStone Architecture External Memory Interface (EMIF16) User Guide SPRUGZ3A—May 2011 Submit Documentation Feedback...

  • Page 57: Nand Flash Error Address 1 Register (Nandfea1R)

    Reserved. The reserved bit location is always read as 0. A value written to this field has no effect ERR_ADDR1 4-Bit error address 1. End of Table 4-18 SPRUGZ3A—May 2011 KeyStone Architecture External Memory Interface (EMIF16) User Guide 4-23 Submit Documentation Feedback...

  • Page 58: Nand Flash Error Address 2 Register (Nandfea2R)

    Reserved. The reserved bit location is always read as 0. A value written to this field has no effect ERR_ADDR3 4-Bit error address 3. End of Table 4-19 4-24 KeyStone Architecture External Memory Interface (EMIF16) User Guide SPRUGZ3A—May 2011 Submit Documentation Feedback...

  • Page 59: Nand Flash Error Value 1 Register (Nandfev1R)

    Reserved. The reserved bit location is always read as 0. A value written to this field has no effect ERR_VAL1 4-Bit error value 1. End of Table 4-20 SPRUGZ3A—May 2011 KeyStone Architecture External Memory Interface (EMIF16) User Guide 4-25 Submit Documentation Feedback...

  • Page 60: Nand Flash Error Value 2 Register (Nandfev2R)

    Reserved. The reserved bit location is always read as 0. A value written to this field has no effect ERR_VAL3 4-Bit error value 3. End of Table 4-21 4-26 KeyStone Architecture External Memory Interface (EMIF16) User Guide SPRUGZ3A—May 2011 Submit Documentation Feedback...
  • Page 61 2-12 byte enables, 2-12 features, Flash Interface, chip select, 1-2, 2-3, 2-6, CLE, clock, Hold, cycles, 2-3, cycles - max number, clocking, idle, command IMCR, 3-10 SPRUGZ3A—May 2011 KeyStone Architecture External Memory Interface (EMIF16) User Guide IX-1 Submit Documentation Feedback...
  • Page 62 NAND mode configuring, NANDFCR, W_STROBE, NANDFSR, WAIT pin, NOR Flash Page Mode, 3-10 Wait Rise (WR) interrupt, WE Strobe Mode, 2-3, 2-12 operating modes, Write Enable, IX-2 KeyStone Architecture External Memory Interface (EMIF16) User Guide SPRUGZ3A—May 2011 Submit Documentation Feedback...
  • Page 63 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

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