Dx Timing For Multichannel Operation - Texas Instruments TMS320DM36 Series User Manual

www.ti.com
2.8.4 DX Enabler: DXENA
The DXENA bit in the serial port control register (SPCR) controls the high-impedance enable on the
MCBSP_DX pin. When DXENA = 1, the McBSP enables extra delay for the MCBSP_DX pin turn-on time.
This feature is useful for McBSP multichannel operations, such as in a time-division multiplexed (TDM)
system. The McBSP supports up to 128 channels in a multichannel operation. These channels can be
driven by different devices in a TDM data communication line, such as the T1/E1 line. In any multichannel
operation where multiple devices transmit over the same MCBSP_DX line, you need to ensure that no two
devices transmit data simultaneously, which results in bus contention. Enough dead time should exist
between the transmission of the first data bit of the current device and the transmission of the last data bit
of the previous device. In other words, the last data bit of the previous device needs to be disabled to a
high-impedance state before the next device begins transmitting data to the same data line, as shown in
Figure 36.
When two McBSPs are used to transmit data over the same TDM line, bus contention occurs if
DXENA = 0. The first McBSP turns off the transmission of the last data bit (changes MCBSP_DX from
valid to a high-impedance state) after a disable time specified in the data manual. As shown in
this disable time is measured from the CLKX active clock edge. The next McBSP turns on its MCBSP_DX
pin (changes from a high-impedance state to valid) after a delay time. Again, this delay time is measured
from the CLKX active clock edge. Bus contention occurs because the dead time between the two devices
is not enough. You need to apply alternative software or hardware methods to ensure proper multichannel
operation in this case.
If you set DXENA = 1 in the second McBSP, the second McBSP turns on its MCBSP_DX pin after some
extra delay time. This ensures that the previous MMcBSP on the same MCBSP_DX line is disabled before
the second McBSP starts driving out data. The MCBSP_DX enabler controls only the high-impedance
enable on the MCBSP_DX pin, not the data itself. Data is shifted out to the MCBSP_DX pin at the same
time as in the case when DXENA = 0. The only difference is that with DXENA = 1, the MCBSP_DX pin is
masked to a high-impedance state for some extra CPU cycles before the data is seen on the TDM data
line. Therefore, only the first bit of data is delayed. Refer to the specific device datasheet for the exact
amount of delay.
CLKX
DX
2.8.5 Using Two Partitions
For multichannel selection operation in the receiver and/or the transmitter, you can use two partitions or
eight partitions. If you choose the 2-partition mode (RMCME = 0 for reception, XMCME = 0 for
transmission), McBSP channels are activated using an alternating scheme. In response to a frame-sync
pulse, the receiver or transmitter begins with the channels in partition A and then alternates between
partitions B and A until the complete frame has been transferred. When the next frame-sync pulse occurs,
the next frame is transferred, beginning with the channels in partition A.
SPRUFI3A – March 2009 – Revised August 2009
Submit Documentation Feedback
Figure 36. DX Timing for Multichannel Operation
Disable time
(processor 0)
Dead time
B0 (processor 0)
TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface
Copyright © 2009–2009, Texas Instruments Incorporated
Extra delay
if DXENA = 1 (processor 1)
No extra delay
even with DXENA = 1
B7 (processor 1) B6 (processor 1)
Peripheral Architecture
Figure 36,
45