Spi Control Register 1 (Spictrl1) - Texas Instruments TMS470R1 series Reference Manual

Control Registers
6.1

SPI Control Register 1 (SPICTRL1)

Bits 31
0x00
Bits 15
Reserved
U
R = Read, W = Write, U = Undefined; -n = Value after reset
Bits 31:13
Bits 12:5
POLARITY PHASE
X 0
X 1
24
13 12
Reserved.
Reads are undefined and writes have no effect.
PRESCALE Determines the bit transfer rate if the SPI is the network master.
There are 255 data transfer rates (each a function of the interface clock) that
can be selected. One data bit is shifted per SPICLK cycle.
SPI Baud Rate for PRESCALE = 1 to 255
SPIBaudRate
SPI Baud Rate for PRESCALE = 0
SPIBaudRate
If the SPI is a network slave, the module receives a clock signal on the
SPICLK pin from the network master. However, the slave's PRESCALE baud
rate (Slave SPICLK) must also conform to the following specifications:
MasterSPICLK
------------------------------------------ -
2
MasterSPICLK
------------------------------------------ -
2
Reserved
U
PRESCALE
RW-0
ICLK
= ------------------------------------------------ -
( )
PRESCALE + 1
ICLK
= ------------- -
2
SPICLK RATIO
≤
SlaveSPICLK
≤
SlaveSPICLK
5 4
CHARLEN
RW-0
≤ ( )
MasterSPICLK 1
+
≤ ( ×
MasterSPICLK 2
16
0
%)
)