Nand Flash Control Register (Nandfcr); Figure - Texas Instruments EMIF16 User Manual

4.12 NAND Flash Control Register (NANDFCR)

Chapter 4—Registers

4.12 NAND Flash Control Register (NANDFCR)

Figure 4-8

NAND Flash Control Register (NANDFCR)
31
Reserved
10
CS4_ECC_START
RW -
5 4
4BIT_ECC_SEL
Table 4-9 NAND Flash Control Register (NANDFCR) Details (Part 1 of 2)
Bit Field
31-14 Reserved
13 ADDR_CALC_START
12 4BIT_ECC_START
11 CS5_ECC_START
10 CS4_ECC_START
9 CS3_ECC_START
8 CS2_ECC_START
7-6 Reserved
4-12 KeyStone Architecture External Memory Interface (EMIF16) User Guide
The NANDFCR register is shown in
R - 0x0
9
CS3_ECC_START
RW -
3
CS5_USE_NAND CS4_USE_NAND
Reset Value
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Figure 4-8
14 13
ADDR_CALC_START
RW -
8
CS2_ECC_START
RW -
2
CS3_USE_NAND
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect
NAND Flash 4-bit ECC error address and error value calculation start.
Set to 1 to start 4-bit ECC error address and error value calculation on read syndrome.
This bit is cleared when any of the NAND Flash Error Address registers or NAND Flash
Error Value registers are read.
Writing a 0 has no effect.
NAND Flash 4-bit ECC start for the selected chip select.
Set to 1 to start 4-bit ECC calculation on data for NAND Flash on chip select selected by
4BIT_ECC_SEL. This bit is cleared when any of the NAND Flash 4-Bit ECC registers are
read.
Writing a 0 has no effect.
NAND Flash 1-bit ECC start for chip select CE3.
Set to 1 to start 1-bit ECC calculation on data for NAND Flash on CE3. This bit is cleared
when NAND Flash CS5 1-Bit ECC register is read.
Writing a 0 has no effect.
NAND Flash 1-bit ECC start for chip select CE2.
Set to 1 to start 1-bit ECC calculation on data for NAND Flash on CE2. This bit is cleared
when NAND Flash CS4 1-Bit ECC register is read.
Writing a 0 has no effect.
NAND Flash 1-bit ECC start for chip select CE1.
Set to 1 to start 1-bit ECC calculation on data for NAND Flash on CE1. This bit is cleared
when NAND Flash CS3 1-Bit ECC register is read.
Writing a 0 has no effect.
NAND Flash 1-bit ECC start for chip select CE0.
Set to 1 to start 1-bit ECC calculation on data for NAND Flash on CE0. This bit is cleared
when NAND Flash CS2 (CE0) 1-Bit ECC register is read.
Writing a 0 has no effect.
Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect
and described in Table 4-9.
12
4BIT_ECC_START CS5_ECC_START
RW -
7
Reserved
RW -
1
CS2_USE_NAND
SPRUGZ3A—May 2011
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11
RW -
6
0