Texas Instruments TMS470R1 series Reference Manual
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Texas Instruments TMS470R1 series Reference Manual

Serial peripheral interface
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TMS470R1x Serial Peripheral Interface
(SPI) Reference Guide
Literature Number: SPNU195E
August 2005

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Summary of Contents for Texas Instruments TMS470R1 series

  • Page 1 TMS470R1x Serial Peripheral Interface (SPI) Reference Guide Literature Number: SPNU195E August 2005...
  • Page 2 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products...
  • Page 3 REVISION HISTORY REVISION DATE NOTES 8/05 Page 16, Baud Rate Limitations section added Page 24, information on slave prescale baud rate added Page 27, note on clearing SPIBUF added...

  • Page 5: Table Of Contents

    Contents Overview ..............2 SPI Operation Modes .
  • Page 6 Figures SPI Module Block Diagram (Five Pin Mode Shown)........3 SPI Three Pin Option .
  • Page 7 Serial Peripheral Interface (SPI) This reference guide provides the specifications for a 16-bit configurable synchronous serial peripheral interface (SPI). The SPI is in effect a programmable-length shift register used for high speed communication between external peripherals or other microcontrollers. Topic Page Overview .

  • Page 8: Overview

    Overview Overview The SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (3 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used for communication between the microcontroller and external peripherals or another microcontroller.

  • Page 9: Spi Operation Modes

    SPI Operation Modes SPI Operation Modes The SPI operates in a master or slave mode. The MASTER bit (SPICTRL2.3) selects the configuration of the SPISIMO and SPISOMI pins and the CLKMOD bit (SPICTRL2.5) determines whether an internal or external clock source will be used.

  • Page 10: Spi Internal Registers

    SPI Operation Modes SPI Internal Registers A general representation of the SPI internal registers is shown in Table 1. The page column provides a cross reference to additional information on the individual registers. For more information regarding individual bytes, see Table , on page Table 1.

  • Page 11: Spi Operation; Three-Pin Option

    SPI Operation Modes SPI Operation; Three-Pin Option In master mode configuration (MASTER = 1 (SPICTRL2.3) and CLKMOD = 1 (SPICTRL2.5)), the SPI provides the serial clock on the SPICLK pin for the entire serial communications network. Data is output on the SPISIMO pin and latched in from the SPISOMI pin (see Figure Figure 2.
  • Page 12 SPI Operation Modes the input for the serial shift clock, which is supplied from the external network master. The transfer rate is defined by this clock. Data written to the SPIDAT0 register is transmitted to the network when the SPICLK signal is received from the network master. To receive data, the SPI waits for the network master to send the SPICLK signal and then shifts data on the SPISIMO pin into the SPIDAT0 register.

  • Page 13: Spi Operation; Four-Pin Option

    SPI Operation Modes SPI Operation; Four-Pin Option The three-pin option and the four-pin options of the SPI are identical in the master mode (CLKMOD = 1), except that the four-pin option uses either SPIENA or SPISCS pin. The I/O direction of these pins is determined by the CLKMOD control bit as SPI not general purpose I/O.

  • Page 14: Spi Four Pin Option With Spiena

    SPI Operation Modes 4-pin option with SPIENA To use the SPIENA as a WAIT signal pin, the SPIENA pin must be configured to be functional (SPIPC6.0 = 1). In this mode, an active low signal on the SPIENA pin will allow the master SPI to drive the clock pulse stream; otherwise, the master will hold the clock signal.

  • Page 15: Spi Operation; Five-Pin Option (Hardware Handshaking)

    SPI Operation Modes SPI Operation; Five-Pin Option (Hardware Handshaking) To use the hardware handshaking mechanism, both the SPIENA pin and SPISCS pin must be configured as functional pins. In the master SPI (CLKMOD = 1), if the SPIENA pin is configured as a functional input.

  • Page 16: Spi Five-Pin Option With Spiena And Spiscs

    SPI Operation Modes Figure 5. SPI Five-Pin Option with SPIENA and SPISCS SPI five pin option Master Slave (Master = 1 ; CLKMOD = 1) (Master = 0 ; CLKMOD = 0) SPISIMO SPISIMO SPISOMI SPISOMI SPIDAT1 SPIDAT0 SPICLK SPICLK SPISCS Write to SPISCS...

  • Page 17: Data Format

    SPI Operation Modes Data Format The data formats for the three, four and five pin options are identical. CHARLEN[4:0] (SPICTRL1.4-0) specifies the number of bits (3 to 16) in the data word. The CHARLEN[4:0] value directs the state control logic to count the number of bits received or transmitted to determine when a complete word is processed.

  • Page 18: Clocking Modes

    SPI Operation Modes Clocking Modes There are four clock modes in which SPICLK may operate, depending on the choice of the phase (delay/no delay) and the polarity (rising edge / falling edge) of the clock. When operating with PHASE active, the SPI makes the first bit of data available after the SPIDAT0 register is written and before the first edge of SPICLK.

  • Page 19: Clock Mode With Polarity = 0 And Phase = 0

    SPI Operation Modes Figure 6. Clock Mode with POLARITY = 0 and PHASE = 0 Clock polarity = 0, Clock phase = 0 Write SPIDAT SPICLK SPISIMO SPISOMI Sample in reception Clock phase = 0 (SPICLK without delay) - Data is output on the rising edge of SPICLK - Input data is latched on the falling edge of SPICLK - A write to the SPIDAT register starts SPICLK Figure 7.

  • Page 20: Clock Mode With Polarity = 1 And Phase = 0

    SPI Operation Modes Figure 8. Clock Mode with POLARITY = 1 and PHASE = 0 Clock polarity = 1, Clock phase = 0 Write SPIDAT SPICLK SPISIMO SPISOMI Sample in reception Clock phase = 0 (SPICLK without delay) - Data is output on the falling edge of SPICLK - Input data is latched on the rising edge of SPICLK - A write to the SPIDAT register starts SPICLK Figure 9.

  • Page 21: Data Transfer Example

    SPI Operation Modes Data Transfer Example The following timing diagram illustrates an SPI data transfer between two devices using a character length of five bits. Figure 10. Five Bits per Character (5-Pin Option) Master SPI Int. flag Slave SPI Int. flag SPISOMI from slave SPISIMO...

  • Page 22: Baud Rate Limitations

    SPI Operation Modes Baud Rate Limitations It is recommended to operate the master and slave SPIs at the same baud rate. However, when this is not possible the SPICLK ranges specified in Table 3 must be followed to ensure proper data transfer. The SPICLK rate is set by adjusting the PRESCALE value in the SPICTRL1 register.

  • Page 23: General Purpose I/O

    General Purpose I/O General Purpose I/O Each of the SPI pins may be programmed via the SPI Pin Control Registers (SPIPC1, SPIPC2, SPIPC3, SPIPC4, SPIPC5, SPIPC6) to be a general- purpose I/O pin. When the SPI module is not used, the SPI pins may be programmed to be either general input or general output pins.

  • Page 24: Low Power Mode

    Low Power Mode Low Power Mode The SPI module has two means to be placed in a low-power mode: a global low-power mode from the system and a local low-power mode via the POWERDOWN bit (SPICTRL2.2). The net effect on the SPI is the same, independent of the source.

  • Page 25: Dma Interface

    DMA Interface DMA Interface If handling the SPI message traffic on a character-by-character basis requires too much CPU overhead and if the particular device is equipped with the DMA controller, the SPI may use the DMA controller to receive or transmit data directly to memory.

  • Page 26: Control Registers

    Control Registers Control Registers This section describes the SPI control, data and pin registers The registers support 16-bit and 32-bit writes.
  • Page 27 Table 4. SPI Registers Offset Address† Register 0x00 SPICTRL1 Reserved Reserved PRESCALE.7:0 CHARLEN.4:0 0x04 SPICTRL2 Reserved POWER POLAR- Reserved MASTER PHASE DOWN 0x08 SPICRTL3 Reserved ENABLE OVRN RCVR RXINT RXINT- Reserved REQ EN HIGHZ INTEN OVRN FLAG 0x0C SPIDAT0 Reserved SPIDAT0.15:0 0x10 SPIDAT1...
  • Page 28 Table 4. SPI Registers (Continued) Offset Address† Register RXINT- 0x14 SPIBUF Reserved FLAG SPIBUF.15:0 0x18 SPIEMU Reserved SPIEMU.15:0 0x1C SPIPC1 Reserved SOMI SIMO ENABLE Reserved 0x20 SPIPC2 Reserved SOMI SIMO ENABLE Reserved 0x24 SPIPC3 Reserved SOMI SIMO ENABLE Reserved DOUT DOUT DOUT DOUT...
  • Page 29 Table 4. SPI Registers (Continued) Offset Address† Register 0x2C SPIPC5 Reserved SOMI SIMO ENABLE Reserved DOUT DOUT DOUT DOUT 0x30 SPIPC6 Reserved SOMI SIMO ENABLE Reserved † The actual addresses of these registers are device specific. See the specific device data sheet to verify the SPI register addresses. ‡...

  • Page 30: Spi Control Register 1 (Spictrl1)

    Control Registers SPI Control Register 1 (SPICTRL1) Bits 0x00 Reserved Bits Reserved PRESCALE CHARLEN RW-0 RW-0 R = Read, W = Write, U = Undefined; -n = Value after reset Bits 31:13 Reserved. Reads are undefined and writes have no effect. Bits 12:5 PRESCALE Determines the bit transfer rate if the SPI is the network master.
  • Page 31 Control Registers Bits 4:0 CHARLEN Controls how many times the SPI shifts per character transmitted or the number of bits per character. The binary value of the bit length must be programmed into this register. Legal values are 0x03 to 0x10. Illegal values, such as 0x00 or 0x1F are not detected and their effect is indeterminate.

  • Page 32: Spi Control Register 2 (Spictrl2)

    Control Registers SPI Control Register 2 (SPICTRL2) Bits 0x04 Reserved Bits MAS- POLA PHAS Reserved RITY RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 R = read; W = Write; U = Undefined; -n = Value after reset Bits 31:6 Reserved. Reads are undefined and writes have no effect. Bit 5 CLKMOD.
  • Page 33 Control Registers Note: Clearing SPIBUF Clearing and then setting the SPIEN bit does not clear an internal flag that indicates that there is valid data in the SPI data register. This could lead to an inadvertent overrun error. The software should do a dummy read of SPIBUF after setting the SPIEN bit to clear the internal flag.

  • Page 34: Spi Control Register 3 (Spictrl3)

    Control Registers SPI Control Register 3 (SPICTRL3) Bits 0x08 Reserved Bits OVRN ABLE RCVR Reserved HIGH OVRN FLAG RW-0 RW-0 RW-0 RC-0 RW-0 RC-0 R = Read, W = Write, C = Clear, U = Undefined; -n = Value after reset Bits 31:6 Reserved.
  • Page 35 Control Registers Bit 2 RCVR OVRN. Receiver overrun flag. This bit is a read/clear only flag. The SPI hardware sets this bit when an operation completes before the previous character has been read from the buffer. The bit indicates that the last received character has been overwritten and therefore lost.

  • Page 36: Spi Shift Register 0 (Spidat0)

    Control Registers SPI Shift Register 0 (SPIDAT0) Bits 0x0C Reserved Bits SPIDAT0 RW-0 R = Read, W = Write, U = Undefined; -n = Value after reset Bits 31:16 Reserved Reads are undefined and writes have no effect. Bits 15:0 SPIDAT0 SPI shift data 0.

  • Page 37: Spi Shift Register 1 (Spidat1)

    Control Registers SPI Shift Register 1 (SPIDAT1) Bits 0x10 Reserved Bits SPIDAT1 RW-0 R = Read, W = Write, U = Undefined; -n = Value after reset Bits 31:16 Reserved Reads are undefined and writes have no effect. Bits 15:0 SPIDAT1 SPI shift data 1.

  • Page 38: Spi Buffer Register (Spibuf)

    Control Registers SPI Buffer Register (SPIBUF) Bits RCVR 0x14 Reserved OVRN FLAG RC-0 RC-0 Bits SPIBUF R = Read, C = Clear, U = Undefined; -n = Value after reset Bits 31:18 Reserved. Reads are undefined and writes have no effect Bit 17 RCVR OVRN IMG.
  • Page 39 Control Registers Bit 16 RXINTFLAG IMG. SPI interrupt flag image. This is a mirror bit of the RXINTFLAG bit (SPICTRL3.0). This bit is cleared in one of four ways. Reading the SPIBUF register Writing a 1 to this bit Writing a 0 to SPIEN (SPICTRL2.4) System reset Interrupt condition did not occur Interrupt condition did occur...

  • Page 40: Spi Emulation Register (Spiemu)

    Control Registers SPI Emulation Register (SPIEMU) Bits 0x18 Reserved Bits SPIEMU R = Read, U = Undefined; -n = Value after reset Bits 31:16 Reserved. Reads are undefined and writes have no effect Bits 15:0 SPIEMU: SPI emulation. SPI emulation is a mirror of the SPIBUF register. The only difference between SPIEMU and SPIBUF is that a read from SPIEMU does not clear the RCVR OVRN (SPICTRL3.2) or RXINTFLAG (SPICTRL3.0) bits.

  • Page 41: Spi Pin Control Register 1 (Spipc1)

    Control Registers SPI Pin Control Register 1 (SPIPC1) Bits 0x1C Reserved Bits SOMI SIMOI Reserved RW-0 RW-0 RW-0 RW-0 RW-0 R = Read, C = Clear, U = Undefined; -n = Value after reset Bits 31:5 Reserved. Reads are undefined and writes have no effect Bit 4 SCS DIR: SPISCS direction.
  • Page 42 Control Registers Bit 1 CLKDIR: SPICLK direction. Controls the direction of the SPICLK pin when it is used as a general-purpose I/O pin. In functional mode, the I/O direction is determined by the CLKMOD bit (SPICTRL2.5). SPICLK pin is an input SPICLK pin is an output Bit 0 ENA DIR: SPIENA direction.

  • Page 43: Spi Pin Control Register 2 (Spipc2)

    Control Registers SPI Pin Control Register 2 (SPIPC2) Bits 0x20 Reserved Bits SOMI SIMO Reserved R = Read, C = Clear, U = Undefined; -n = Value after reset Bits 31:5 Reserved. Write: Has no effect Read: Value is indeterminate Reset: Undefined Bit 4 SCS DIN: SPISCS data in.
  • Page 44 Control Registers Bit 0 ENA DIN: SPIENA data in. Reflects the value of the SPIENA pin. Current value on SPIENA pin is logic 0. Current value on SPIENA pin is logic 1...

  • Page 45: Spi Pin Control Register 3 (Spipc3)

    Control Registers 6.10 SPI Pin Control Register 3 (SPIPC3) Bits 0x24 Reserved Bits SOMI SIMO Reserved DOUT DOUT DOUT DOUT DOUT RW-0 RW-0 RW-0 RW-0 RW-0 R = Read, W = Write, U = Undefined; -n = Value after reset Bits 31:5 Reserved.
  • Page 46 Control Registers Bit 1 CLK DOUT: SPICLK dataout write. Only active when the SPICLK pin is configured as a general-purpose I/O pin and configured as an output pin. The value of this bit indicates the value sent to the pin. Current value on SPICLK pin is logic 0.

  • Page 47: Spi Pin Control Register 4 (Spipc4)

    Control Registers 6.11 SPI Pin Control Register 4 (SPIPC4) Bits 0x28 Reserved Bits SOMI SIMO Reserved DSET DSET DSET DSET DSET RW-0 RW-0 RW-0 RW-0 RW-0 R = Read, W = Write, U = Undefined; -n = Value after reset Bits 31:5 Reserved.
  • Page 48 Control Registers Bit 2 SIMO DSET: SPISIMO dataout set. Only active when the SPISIMO pin is configured as a general-purpose output pin. A value of one written to this bit sets the corresponding SPISIMODOUT bit (SPIPC3.2) to one. Write: Has no effect Logic 1 placed on SPISIMO pin Read: Current value on SPISIMO pin is logic 0.

  • Page 49: Spi Pin Control Register 5 (Spipc5)

    Control Registers 6.12 SPI Pin Control Register 5 (SPIPC5) Bits 0x2C Reserved Bits SOMI SIMO Reserved DCLR DCLR DCLR DCLR DCLR RW-0 RW-0 RW-0 RW-0 RW-0 R = Read, W = Write, U = Undefined; -n = Value after reset Bits 31:5 Reserved.
  • Page 50 Control Registers Bit 2 SIMO DCLR: SPISIMO dataout clear. Only active when the SPISIMO pin is configured as a general-purpose output pin. A value of one written to this bit clears the corresponding SPISIMODOUT bit (SPIPC3.2) to zero. Write: Has no effect Logic 0 placed on SPISIMO pin Read: Current value on SPISIMO pin is logic 0.

  • Page 51: Spi Pin Control Register 6 (Spipc6)

    Control Registers 6.13 SPI Pin Control Register 6 (SPIPC6) Bits 0x30 Reserved Bits SOMI SIMO Reserved RW-0 RW-0 RW-0 RW-0 RW-0 R = Read, W = Write, U = Undefined; -n = Value after reset Bits 31:5 Reserved. Reads are undefined and writes have no effect Bit 4 SCS FUN: SPISCS function.
  • Page 52 Control Registers Bit 0 ENA FUN: SPIENA function. Determines whether the SPIENA pin is to be used as a general-purpose I/O pin, or as a SPI functional pin. SPIENA pin is a GPIO SPIENA pin is a SPI functional pin...

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