Texas Instruments TMS320DM36 Series User Manual
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Texas Instruments TMS320DM36 Series User Manual

Texas Instruments TMS320DM36 Series User Manual

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TMS320DM36x DMSoC
Multichannel Buffered Serial Port (McBSP)
Interface
User's Guide
Literature Number: SPRUFI3A
March 2009 – Revised August 2009

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Summary of Contents for Texas Instruments TMS320DM36 Series

  • Page 1 TMS320DM36x DMSoC Multichannel Buffered Serial Port (McBSP) Interface User's Guide Literature Number: SPRUFI3A March 2009 – Revised August 2009...
  • Page 2 SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 3: Table Of Contents

    Enhanced Receive Channel Enable Registers (RCERE0-RCERE3) ........... Enhanced Transmit Channel Enable Registers (XCERE0-XCERE3) ................... 3.10 Pin Control Register (PCR) ...................... Appendix A Revision History SPRUFI3A – March 2009 – Revised August 2009 Table of Contents Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 4 SPI Transfer With CLKSTP = 3h (clock delay) and CLKXP = 1 ....................McBSP as the SPI Master ................... Data Receive Register (DRR) List of Figures SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 5 Enhanced Receive Channel Enable Register n (RCEREn) ............Enhanced Transmit Channel Enable Register n (XCEREn) ....................Pin Control Register (PCR) SPRUFI3A – March 2009 – Revised August 2009 List of Figures Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 6 Enhanced Transmit Channel Enable Register n (XCEREn) Field Descriptions ............... Use of the Transmit Channel Enable Registers ................ Pin Control Register (PCR) Field Descriptions ....................Document Revision History List of Tables SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 7: Preface

    DMSoC and external peripherals. Typical applications include an interface to external I/O or peripheral expansion via devices such as shift registers, display drivers, SPI EPROMs and analog-to-digital converters. SPRUFI3A – March 2009 – Revised August 2009 Preface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 8 (UHPI) User's Guide This document describes the operation of the universal host port interface in the TMS320DM36x Digital Media System-on-Chip (DMSoC). Read This First SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 9 TMS320DM36x Digital Media System-on-Chip (DMSoC). SPI is a trademark of Motorola, Inc.. SPRUFI3A – March 2009 – Revised August 2009 Read This First Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 10: Introduction

    Programmable polarity for both frame synchronization and data clocks • Highly programmable internal clock and frame generation TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 11: Functional Block Diagram

    The IIS bus is an industry standard three-wire interface for streaming stereo audio between devices, typically between an ARM and a DAC/ADC. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 12: Peripheral Architecture

    McBSP. Endianness Considerations There are no endianness considerations for the McBSP. TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 13: Clock, Frames, And Data

    FS(R/X)P = 1, before being sent to the FS(R/X) pin.Figure 2 shows this inversion using XOR gates. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 14: Transmit Data Clocking

    Figure 3. Transmit Data Clocking CLKX_int Propagation Disable time delay Figure 4. Receive Data Clocking CLKR_int Data setup Data hold TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 15: Sample Rate Generator Block Diagram

    MCBSP_CLKR pin CLKRP CLKG MCBSP_CLKX pin CLKXP SCLKME, CLKSM Frame pulse detection GSYNC and clock synchronization MCBSP_FSR SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 16: Choosing An Input Clock For The Sample Rate Generator With The Sclkme And Clksm Bits

    The following equation is given above: f /(CLKGDV + 1); therefore, S = (CLKGDV + 1) × S TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 17 CLKG runs freely and is not resynchronized. If GSYNC = 1, an inactive-to-active transition on FSR triggers SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 18: Clkg Synchronization And Fsg Generation When Gsync = 1 And Clkgdv

    FSR external (FSRP = 0) FSR external (FSRP = 1) CLKG (no need to resync) CLKG (needs resync) TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 19: Clkg Synchronization And Fsg Generation When Gsync = 1 And Clkgdv

    CLKRM determines whether the MCBSP_CLKR pin is an input or an output. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 20: Receive Clock Selection

    Output. CLKR (same as CLKX) is inverted as inverted. determined by CLKRP before being driven out. TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 21: Transmit Clock Selection

    The FWID bits in SRGR are an 8-bit down-counter. FWID controls the active width of the frame sync pulse. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 22: Programmable Frame Period And Width

    The three choices are: TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 23 FRLEN and WDLEN bits, respectively) is valid as long as their product is less than or equal to 4096 bits. This limitation does not apply for dual-phase with external frame sync. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 24: Dual-Phase Frame Example

    (R/X)WDLEN2 is not used by the McBSP and its value does not matter. TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 25: Single-Phase Frame Of Four 8-Bit Elements

    (Figure 11). This manipulation reduces the percentage of bus time required for serial port data movement. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 26: Single-Phase Frame Of One 32-Bit Element

    FSX goes active, and it immediately starts driving the first bit to be transmitted on the MCBSP_DX pin. TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 27: Effect Of Rjust Bit Values With 12-Bit Example Data Abch

    Zero-fill MSBs 000A BCDEh Right Sign-extend MSBs FFFA BCDEh Left Zero-fill LSBs ABCD E000h Reserved Reserved Reserved SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 28: Mcbsp Standard Operation

    CPU or the EDMA controller. RRDY is deactivated when the DRR is read by the CPU or the EDMA controller. See also Section 2.12.1.2 Section 2.13.1. TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 29: Receive Operation

    CLKX XRDY DXR to XSR copy Write of DXR DXR to XSR copy Write of DXR SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 30: Maximum Frame Frequency For Transmit And Receive

    8-bit clocks. This situation can be resolved by allowing additional space between words or choosing a slower bit clock (larger CLKGDV value). TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 31: Unexpected Frame Synchronization With (R/X)Fig

    Figure 19. Unexpected Frame Synchronization With (R/X)FIG = 0 CLK(R/X) Frame sync aborts current transfer FS(R/X) New data received Current data retransmitted (R/X)SYNCERR SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 32: Unexpected Frame Synchronization With (R/X)Fig

    8-bit blocks. TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 33: Maximum Frame Frequency Operation With 8-Bit Data

    Receive overrun (RFULL = 1 in SPCR) • Unexpected receive frame synchronization (RSYNCERR = 1 in SPCR) SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 34 This data loss can be avoided if DRR is read no later than two and a half CLKR cycles before the end of the third element (data C) in RSR, as shown in Figure TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 35: Serial Port Receive Overrun

    No Read of DRR (A) No RBR-to-DRR copy (B) Read of DRR (A) RFULL RBR-to-DRR copy (A) RBR-to-DRR (B) SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 36 NOTE: Note that the RSYNCERR bit in SPCR is a read/write bit, so writing a 1 to it sets the error condition. Typically, writing a 0 is expected. TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 37: Decision Tree Response To Receive Frame Synchronization Pulse

    DXR or by waiting for a programmed XINT to be triggered by XRDY (XINTM = 00b). The EDMA controller can avoid overwriting by synchronizing data writes with XEVT. See also Section 2.12.1.3. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 38: Transmit With Data Overwrite

    DXR-to-XSR copy (B) Write of DXR (C) Write of DXR (D) DXR-to-XSR copy (D) Write of DXR (E) TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 39: Transmit Empty

    Figure 29. Transmit Empty Avoided CLKX XRDY Write of DXR (C) DXR-to-XSR copy (B) DXR-to-XSR copy (C) XEMPTY SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 40 NOTE: The XSYNCERR bit in SPCR is a read/write bit, so writing a 1 to it sets the error condition. Typically, writing a 0 is expected. TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 41: Μ-Law/A-Law Companding Hardware Operation

    8-bit element length, companding continues as if the element length is eight bits. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 42: Companding Flow

    Table 12. Justification of Expanded Data in DRR DRR Bits RJUST Bit in SPCR LAW16 sign LAW16 LAW16 Reserved TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 43: Companding Of Internal Data

    (R/X)WDLEN1/2 bit is cleared to 0, indicating that 8-bit elements are to be serially transferred. A 32-bit bit reversal feature is also available, as shown in Section 2.5.5.7 SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 44: Multichannel Selection Modes

    TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 45: Dx Timing For Multichannel Operation

    B and A until the complete frame has been transferred. When the next frame-sync pulse occurs, the next frame is transferred, beginning with the channels in partition A. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 46: Receive Channel Assignment And Control When Two Receive Partitions Are Used

    Block 5: channels 80 through 95 – XCE16-XCE31 Block 7: channels 112 through 127 – XCE16-XCE31 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 47: Alternating Between The Channels Of Partition A And The Channels Of Partition B

    Block 7 assigned Block 1 assigned to partition B to partition B to partition B to partition B SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 48: Mcbsp Data Transfer In The 8-Partition Mode

    Figure 39. McBSP Data Transfer in the 8-Partition Mode 8-partition mode Partition Block Channels 0-15 16-31 32-47 48-63 64-79 80-95 96-111 112-127 0-15 FS(R/X) TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 49: Selecting A Transmit Multichannel Selection Mode With The Xmcm Bits

    4. Places the MCBSP_DX pin in the high-impedance state in channels 16–38. 5. Shifts data to the MCBSP_DX pin in channel 39. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 50 40, the arrows showing where the various events occur are only sample indications. Wherever possible, there is a time window in which these events can occur. TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 51: Activity On Mcbsp Pins For The Possible Values Of Xmcm

    RBR to DRR (W3) XRDY DXR to XSR copy (W1) Write to DXR(W3) DXR to XSR copy (W3) SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 52: Spi Operation Using The Clock Stop Mode

    SS signal is not used by the slave SPI port, the slave device must remain enabled at all times, and multiple slaves cannot be used. TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 53: Bits Used To Enable And Configure The Clock Stop Mode

    High inactive state with delay: The McBSP transmits data one-half cycle ahead of the falling edge of CLKX and receives data on the falling edge of CLKR. See Figure SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 54: Spi Transfer With Clkstp = 2H (No Clock Delay) And Clkxp

    1) McBSP is SPI master (CLKXM = 1), MOSI = DX 2) McBSP is SPI master (CLKXM = 1), MISO = DR TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 55: Spi Transfer With Clkstp = 2H (No Clock Delay) And Clkxp

    1) McBSP is SPI master (CLKXM = 1), MOSI = DX 2) McBSP is SPI master (CLKXM = 1), MISO = DR SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 56 (DXR is loaded with data), set the FRST bit in SPCR to 1 if an internally generated frame-sync pulse is required (that is, if the McBSP is the SPI master). TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 57: Mcbsp As The Spi Master

    RDATDLY = 1 This setting provides the correct setup time on the FSX signal, 1-bit data delay. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 58 After the packet transfer is complete, the FSX signal returns to the inactive state. TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 59: 2.10 Resetting The Serial Port: Rrst, Xrst, Grst, And Reset

    (RRST = XRST = FRST = GRST = 0 in SPCR). SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 60: 2.11 Mcbsp Initialization Procedure

    1. With the McBSP still in reset (Power and Sleep Controller (PSC) in the default state): (a) Program the necessary device pin multiplexing setup (see the device-specific data manual). TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 61 11. Set the FRST bit to 1 to start the internal frame sync generator. The internal frame sync signal FSG is generated on a CLKG active edge after 7 to 8 CLKG clocks have elapsed. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 62 FSG (GRST = FRST = 0 in SPCR). The respective portion of the McBSP needs to be in reset (XRST = 0 and/or RRST = 0 in SPCR). TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 63 10. Upon detection of the second frame sync, DXR is already serviced and the transmitter is ready to transmit the valid data. The receiver is also serviced properly by the processor. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 64: 2.12 Interrupt Support

    XRDY transitions occur based on bit clock and not CPU clock. The CPU clock is much faster and can cause false XRDY status, leading to data errors due to overwrites. TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 65: 2.13 Edma Event Support

    XRDY transitions occur based on bit clock and not CPU clock. The CPU clock is much faster and can cause false XRDY status, leading to data errors due to overwrites. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 66: 2.14 Power Management

    Free run mode. The transmitter and receiver continue to run when an emulation suspend event occurs. TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 67: Registers

    The CPUs and EDMA controller can only read this register; they cannot write to it. The DRR and DXR are accessible via the CPUs or the EDMA controller. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 68: Data Receive Register (Drr)

    0-FFFF FFFFh Data transmit register value to be loaded into the data transmit shift register (XSR). TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 69: Serial Port Control Register (Spcr)

    XINT is driven by XRDY (end-of-word). Reserved XINT is generated by a new frame synchronization. XINT is generated by XSYNCERR. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 70 RBR is not in overrun condition. DRR is not read, RBR is full, and RSR is also full with new word. TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 71: Receive Control Register (Rcr)

    Receive word length is 20 bits. Receive word length is 24 bits. Receive word length is 32 bits. 6h-7h Reserved SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 72 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 73: Transmit Control Register (Xcr)

    Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 74 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 75: Sample Rate Generator Register (Srgr)

    Frame width value plus 1 specifies the width of the frame-sync pulse (FSG) during its active period. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 76: Multichannel Control Register (Mcr)

    XCERE0: Channels 0 through 31 XCERE1: Channels 32 through 63 XCERE2: Channels 64 through 95 XCERE3: Channels 96 through 127 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 77 Block 5: channels 80 through 95 Block 6: channels 96 through 111 Block 7: channels 112 through 127 SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 78 Block 3: channels 48 through 63 Block 5: channels 80 through 95 Block 7: channels 112 through 127 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 79 (RCEREn). The way channels are assigned to RCEREn depends on the number of receive channel partitions (2 or 8), as defined by the RMCME bit. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 80: Enhanced Receive Channel Enable Registers (Rcere0-Rcere3)

    Disable the channel that is mapped to RCEn. Enable the channel that is mapped to RCEn. TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 81: Use Of The Receive Channel Enable Registers

    0, 2, 4, or 6. m is any odd-numbered block 1, 3, 5, or 7. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 82: Enhanced Transmit Channel Enable Registers (Xcere0-Xcere3)

    Unmask the channel that is mapped to XCEn. Even if this channel is also enabled by the corresponding enhanced receive channel enable bit, full transmission can occur. TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 83: Use Of The Transmit Channel Enable Registers

    0, 2, 4, or 6. m is any odd-numbered block 1, 3, 5, or 7. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 84: Pin Control Register (Pcr)

    McBSP is a master and generates the clock (CLKX) to drive its receive clock (CLKR) and the shift clock of the SPI-compliant slaves in the system. TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...
  • Page 85 Receive data sampled on falling edge of CLKR. Receive data sampled on rising edge of CLKR. SPRUFI3A – March 2009 – Revised August 2009 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

  • Page 86: Appendix A Revision History

    Changed all isntances of DX to MCBSP_DX Changed all instances of FSR to MCBSP_FSR Changed all instances of FSX to MCBSP_FSX Revision History SPRUFI3A – March 2009 – Revised August 2009 Submit Documentation Feedback Copyright © 2009–2009, Texas Instruments Incorporated...

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