Mibspi Control Register 1 (Spictrl1) - Texas Instruments TMS470R1x Reference Manual

7.3

MibSPI Control Register 1 (SPICTRL1)

Bits 31
0x00
Bits 15 14
WAITENA0 PARITY0 Reserved
RWP-0 RWP-0
Legend: R = Read, W = write, P = Privilege mode U = Undefined; -n = Value after reset
Bits 31:16 Reserved.
Reads are undefined and writes have no effect.
Bit 15 WAITENA0. Master waits for ENA signal from slave for data format 0
WAITENA is considered in master mode only. In slave mode this bit has no
meaning. WAITENA enables a flexible SPI network where slaves with ENA
signal and slaves without ENA signal can be mixed. WAITENA defines for
each buffer whether the addressed slave generates the ENA signal or does
not.
1 = Before the MibSPI starts the data transfer it waits for the ENA signal to
0 = The MibSPI does not wait for the ENA signal from the slaves and directly
Note:
This bit is only accessible in MibSPI mode
Bit 14 PARITY0. Parity enable for data format 0.
1 = A parity is added after transfer of the data bit. At the end of a transfer the
0 = No parity generation/ verification is performed for this data format.
Note:
This bit is only accessible in MibSPI mode
Bits 13 Reserved.
Reads are undefined and writes have no effect.
Reserved
U
13 12
PRESCALE
U RW-0
become low. If the ENA signal is not pulled down by the addressed
slave before the internal time-out counter (CE2DELAY) expires.
starts the transfer.
parity generator compares the received parity bit with the locally calcu-
lated parity flag. If the parity bits do not match the RXERR flag is set in
the corresponding control field. The parity type (even or odd) can be
selected via the PARPOL bit (SPICTRL2.6).
Multi-Buffer Serial Peripheral Interface (MibSPI) (SPNU217B)
Control Registers and RAM
16
5 4 0
CHARLEN
RW-0
39