Texas Instruments TMS320C6452 User Manual
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Texas Instruments TMS320C6452 User Manual

Dsp host port interface (hpi)
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TMS320C6452 DSP
Host Port Interface (HPI)
User's Guide
Literature Number: SPRUF87A
October 2007 – Revised May 2008

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Summary of Contents for Texas Instruments TMS320C6452

  • Page 1 TMS320C6452 DSP Host Port Interface (HPI) User's Guide Literature Number: SPRUF87A October 2007 – Revised May 2008...
  • Page 2 SPRUF87A – October 2007 – Revised May 2008 Submit Documentation Feedback...

  • Page 3: Table Of Contents

    Contents ............................Preface ......................... Introduction ....................Purpose of the Peripheral ........................Features ....................Functional Block Diagram ................ Industry Standard(s) Compliance Statement ................. Terminology Used in This Document ....................... Peripheral Architecture ......................Clock Control ......................Memory Map ...................... Signal Descriptions ......................Pin Multiplexing .....................
  • Page 4 www.ti.com List of Figures ......................HPI Block Diagram ............... Example of Host-Processor Signal Connections ....................HPI Strobe and Select Logic ................16-bit Multiplexed-Mode Host Read Cycle ................16-bit Multiplexed-Mode Host Write Cycle ............ Multiplexed-Mode Single-Halfword HPIC Cycle (Read or Write) ......
  • Page 5 www.ti.com List of Tables ........................HPI Pins .............. Options for Connecting Host and HPI Data Strobe Pins ..............Access Types Selectable With the HCNTL Signals ............Cycle Types Selectable With the HCNTL and HR/W Signals ..............HPI Registers Relative to Base Address 0200 0030h ............

  • Page 6: Preface

    SPRUF87A – October 2007 – Revised May 2008 Read This First About This Manual This document describes the features and operation of the host port interface (HPI) in the TMS320C6452 Digital Signal Processor (DSP). Notational Conventions This document uses the following conventions.
  • Page 7 — C6452 DSP Host Port Interface (UHPI) User's Guide describes the host port interface (HPI) in the TMS320C6452 Digital Signal Processor (DSP). The HPI is a parallel port through which a host processor can directly access the CPU memory space. The host device functions as a master to the interface, which increases ease of access.
  • Page 8 SPRUF97 — TMS320C6452 DSP 3 Port Switch (3PSW) Ethernet Subsystem User's Guide describes the operation of the 3 port switch (3PSW) ethernet subsystem in the TMS320C6452 Digital Signal Processor (DSP). The 3 port switch gigabit ethernet subsystem provides ethernet packet communication and can be configured as an ethernet switch.

  • Page 9: Introduction

    The host port interface (HPI) provides a parallel port interface through which an external host processor can directly access the TMS320C6452 processor's resources (configuration and program/data memories). The external host device is asynchronous to the CPU clock and functions as a master to the HPI interface.

  • Page 10: Functional Block Diagram

    Introduction www.ti.com Functional Block Diagram Figure 1 is a high-level block diagram showing how the HPI connects a host (left side of figure) and the processor internal memory (right side of figure). Host activity is asynchronous to the internal processor clock that drives the HPI.

  • Page 11: Industry Standard(S) Compliance Statement

    Introduction www.ti.com Figure 1. HPI Block Diagram Host Processor HD[15:0] Data HPID R/W FIFOs HHWIL Processor HCNTL0 Address memory Access or I/O HPIA HCNTL1 type Logic Increment high HPIC HR/W Chip select Data HDS1 , HDS2 strobes HINT Ready HRDY Industry Standard(s) Compliance Statement The HPI is not an industry standard interface that is developed and monitored by an international organization.

  • Page 12: Peripheral Architecture

    Peripheral Architecture www.ti.com Peripheral Architecture Clock Control The HPI clock is derived from SYSCLK2, which is the PLL1 clock divided by 6. For detailed information on the PLLs and clock distribution on the processor, see the Subsystem User's Guide. Memory Map The HPI can be used by the host to access the following processor resources: •...

  • Page 13: Hpi Pins

    Peripheral Architecture www.ti.com Table 1. HPI Pins Type Host Connection Function HCNTL[1:0] Address or control pins HPI access control inputs. The HPI latches the logic levels of these pins on the falling edge of internal HSTRB (for details about internal HSTRB, Section 2.7.4).

  • Page 14: Architecture And Operation

    Peripheral Architecture www.ti.com Architecture and Operation 2.7.1 Using the Address Registers The HPI contains two 32-bit address registers: one for read operations (HPIAR) and one for write operations (HPIAW). These roles are unchanging from the viewpoint of the HPI logic. The HPI DMA logic gets the address from HPIAR when reading from processor resources (see Section 2.2) and gets the...

  • Page 15: Example Of Host-Processor Signal Connections

    Peripheral Architecture www.ti.com 2.7.2 Host-HPI Signal Connections Figure 2 shows an example of a signal connection between the HPI and a host. Figure 2. Example of Host-Processor Signal Connections Host Processor Logic high HCNTL[1:0] Address or I/O HHWIL HR/W Read/Write Chip select Data strobe 1 HDS1...

  • Page 16: Hpi Strobe And Select Logic

    Peripheral Architecture www.ti.com If the host wants to read data from processor resources (see Section 2.2), the HPI DMA logic reads the resource address from HPIAR and retrieves the data from the addressed memory location. When the data has been placed in HPID, the HPI drives the data onto its HD bus. The HRDY signal informs the host whether the data on the HD bus is valid (HRDY low) or not valid yet (HRDY high).

  • Page 17: Options For Connecting Host And Hpi Data Strobe Pins

    Peripheral Architecture www.ti.com Table 2. Options for Connecting Host and HPI Data Strobe Pins Available Host Data Strobe Pins Connections to HPI Data Strobe Pins Host has separate read and write strobe Connect one strobe pin to HDS1 and the other to HDS2 .

  • Page 18: Cycle Types Selectable With The Hcntl And Hr/W Signals

    Peripheral Architecture www.ti.com Table 4. Cycle Types Selectable With the HCNTL and HR/W Signals HCNTL1 HCNTL0 HR/W Cycle Type HPIC write cycle HPIC read cycle HPID write cycle with auto-incrementing HPID read cycle with auto-incrementing HPIA write cycle HPIA read cycle HPID write cycle without auto-incrementing HPID read cycle without auto-incrementing Note that the encoding of HCNTL0 and HCNTL1 for the different types of HPI accesses varies on many TI DSPs;...

  • Page 19: Bit Multiplexed-Mode Host Read Cycle

    Peripheral Architecture www.ti.com 2.7.7 Performing a Multiplexed Access Figure 2 shows an example of signal connections for multiplexed transfers. Figure 4 Figure 5 show typical HPI signal activity when performing a read and write transfer, respectively. In these cases, the falling edge of internal HSTRB is used to latch the HCNTL[1:0], HR/W, and HHWIL states into the HPI.

  • Page 20: Bit Multiplexed-Mode Host Write Cycle

    Peripheral Architecture www.ti.com Figure 5. 16-bit Multiplexed-Mode Host Write Cycle Internal HSTRB HR/W HCNTL[1:0] HD[15:0] Data 1 Data 2 HRDY HHWIL HPI latches HPI latches control information control information HPI latches HPI latches data data NOTE: Depending on the type of write operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur.

  • Page 21: Multiplexed-Mode Single-Halfword Hpic Cycle (Read Or Write)

    Peripheral Architecture www.ti.com 2.7.8 Single-Halfword HPIC Cycle in 16-bit Multiplexed Mode Figure 6 shows the special case (see Section 2.7.6) when the host performs a single-halfword cycle to access the HPIC. The state of HHWIL is ignored and if a dual-halfword access is performed, then the same HPIC register is accessed twice.

  • Page 22: Hrdy Behavior During An Hpic Or Hpia Read Cycle In The 16-Bit Multiplexed Mode

    Peripheral Architecture www.ti.com 2.7.9.1 HRDY Behavior During 16-bit Multiplexed-Mode Read Operations Figure 7 shows an HPIC (HCNTL[1:0] = 00b) or HPIA (HCNTL[1:0] = 10b) read cycle. Neither an HPIC read cycle nor an HPIA read cycle causes HRDY to go low. For this type of access, the state of HHWIL is ignored, so if a dual halfword access is performed, the same register will be accessed twice.

  • Page 23: Hrdy Behavior During A Data Read Operation In The 16-Bit Multiplexed Mode (Case 2: Hpia Write Cycle Followed By Auto-Increment Hpid Read Cycles)

    Peripheral Architecture www.ti.com Figure 9. HRDY Behavior During a Data Read Operation in the 16-bit Multiplexed Mode (Case 2: HPIA Write Cycle Followed by Auto-increment HPID Read Cycles) HCNTL[1:0] HR/W HHWIL Internal HSTRB 1st halfword 2nd halfword 1st halfword 2nd halfword 1st halfword HD[15:0] HRDY...

  • Page 24: Hrdy Behavior During A Data Write Operation In The 16-Bit Multiplexed Mode (Case 1: No Auto-Incrementing)

    Peripheral Architecture www.ti.com Figure 11. HRDY Behavior During a Data Write Operation in the 16-bit Multiplexed Mode (Case 1: No Auto-incrementing) HCNTL[1:0] HR/W HHWIL Internal HSTRB 1st halfword 2nd halfword 1st halfword 2nd halfword HD[15:0] HRDY Figure 12 shows auto-increment HPID write cycles when the write FIFO is empty prior to the HPIA write. The host writes the memory address while HCNTL[1:0] = 10b and writes the data while HCNTL[1:0] = 01b.

  • Page 25: Hrdy Behavior During An Hpic Or Hpia Read Cycle In The 32-Bit Multiplexed Mode

    Peripheral Architecture www.ti.com 2.7.9.3 HRDY Behavior During 32-bit Multiplexed-Mode Read Operations Figure 14 shows an HPIC (HCNTL[1:0] = 00b) read or an HPIA (HCNTL[1:0] = 01b) read access for 32-bit multiplexed HPI operation. Note that neither an HPIC nor an HPIA read access causes HRDY to become active.

  • Page 26: Hrdy Behavior During A Data Read Operation In The 32-Bit Multiplexed Mode

    Peripheral Architecture www.ti.com Figure 16. HRDY Behavior During a Data Read Operation in the 32-Bit Multiplexed Mode (Case 2: HPIA Write Cycle Followed by Auto-increment HPID Read Cycles) HPIA Write HPID+ Reads HCNTL[1:0] HR/W Internal HSTRB HD[31:0] HRDY 2.7.9.4 HRDY Behavior During 32-bit Multiplexed-Mode Write Operations Figure 17 shows an HPIC (HCNTL[1:0] = 00b) write access for 32-bit multiplexed HPI operation.

  • Page 27: Hrdy Behavior During A Data Write Operation In The 32-Bit Multiplexed Mode (Case 1: No Auto-Incrementing)

    Peripheral Architecture www.ti.com Figure 18. HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 1: No Auto-incrementing) HPIA Write HPID Write HCNTL[1:0] HR/W Internal HSTRB HD[31:0] HRDY Figure 19 shows an HPIA (HCNTL[1:0] = 10b) write access followed by several auto-incrementing HPID (HCNTL[1:0] = 01b) write accesses when the write FIFO is empty.

  • Page 28: Hrdy Behavior During A Data Write Operation In The 32-Bit Multiplexed Mode (Case 3: Auto-Incrementing Selected, Fifo Not Empty Before Write)

    Peripheral Architecture www.ti.com Figure 20. HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 3: Auto-incrementing Selected, FIFO Not Empty Before Write) HPIA Write HPID+ Writes HCNTL[1:0] HR/W Internal HSTRB HD[31:0] HRDY 2.7.10 FIFOs and Bursting The HPI data register (HPID) is a port through which the host accesses two first-in, first-out buffers (FIFOs).

  • Page 29: Fifos In The Hpi

    Peripheral Architecture www.ti.com Figure 21. FIFOs in the HPI Write FIFO control logic Host write HPI DMA pointer read pointer Burst writes Host writes Write FIFO Processor logic memory Read FIFO Burst reads Host reads Host read HPI DMA pointer write pointer Read FIFO control logic...
  • Page 30 Peripheral Architecture www.ti.com Both types of continuous or burst reads described in the previous paragraphs begin with a write to the HPI address register, which causes a read FIFO flush. This is the typical way of initiating read cycles, because the initial read address needs to be specified.

  • Page 31: Reset Considerations

    Peripheral Architecture www.ti.com Similarly, when a write FIFO flush condition occurs, all current host accesses and DMAs to the write FIFO are allowed to complete. This includes DMAs that have been requested but not yet initiated. All posted writes in the FIFO are then forced to completion with a final burst or single-word write, as necessary. If the host initiates an HPID host cycle during a FIFO flush, the cycle is held off with the de-assertion of HRDY until the flush is complete and the FIFO is ready to be accessed.

  • Page 32: Initialization

    Peripheral Architecture www.ti.com • If internal HSTRB is low (host cycle is active), HRDY is driven high, allowing the host to complete the cycle. When internal HSTRB goes high (cycle is complete), HRDY is driven low and remains low until the reset condition is over.

  • Page 33: Cpu-To-Host Interrupt State Diagram

    Peripheral Architecture www.ti.com 2. Write 1 to the DSPINT bit in HPIC. When the host sets the DSPINT bit, the HPI generates an interrupt pulse to the CPU. If this maskable interrupt is properly enabled in the CPU, the CPU executes the corresponding interrupt service routine (ISR).

  • Page 34: 2.11 Edma Event Support

    Peripheral Architecture www.ti.com 2.10.3 Interrupt Multiplexing The HPI has a single interrupt source to the DSP CPU. This interrupt source is not multiplexed with any other interrupt source on the CPU. 2.11 EDMA Event Support The HPI does not provide synchronization events to the EDMA system. Memory accesses from the HPI are handled automatically, independent of the EDMA controller.

  • Page 35: Registers

    Registers www.ti.com Registers Table 5 lists the memory-mapped registers for the HPI. See the device-specific data manual for the memory addresses of these registers. Table 5. HPI Registers Relative to Base Address 0200 0030h Offset Acronym Register Description Section Peripheral Identification Register Section 3.1 PWREMU_MGMT Power and Emulation Management Register...

  • Page 36: Power And Emulation Management Register (Pwremu_Mgmt)

    Registers www.ti.com Power and Emulation Management Register (PWREMU_MGMT) The power and emulation management register (PWREMU_MGMT) determines the emulation mode of the HPI. PWREMU_MGMT is shown in Figure 25 and described in Table Figure 25. Power and Emulation Management Register (PWREMU_MGMT) Reserved Reserved SOFT...

  • Page 37: Host Port Interface Control Register (Hpic)

    Registers www.ti.com Host Port Interface Control Register (HPIC) The host port interface control register (HPIC) stores configuration and control information for the HPI. As shown in Figure 26 Figure 27 and described in Table 8, the owner (Host) and non-owner (DSP) do not have the same access permissions.

  • Page 38: Host Port Interface Control Register (Hpic) Field Descriptions

    Registers www.ti.com Table 8. Host Port Interface Control Register (HPIC) Field Descriptions Field Value Description 31-12 Reserved Reserved HPIASEL HPI address register select bit. When DUALHPIA = 1, the HPIASEL bit is used to select the HPI address register to be accessed. Selects the HPI write address register (HPIAW).

  • Page 39: Host Port Interface Write Address Register (Hpiaw)

    Registers www.ti.com Host Port Interface Write Address Register (HPIAW) The HPI contains two 32-bit address registers: one for read operations (HPIAR) and one for write operations (HPIAW). The host port interface write address register (HPIAW) is shown in Figure 28 described in Table 9.

  • Page 40: Host Port Interface Read Address Register (Hpiar)

    Registers www.ti.com Host Port Interface Read Address Register (HPIAR) The HPI contains two 32-bit address registers: one for read operations (HPIAR) and one for write operations (HPIAW). The host port interface read address register (HPIAR) is shown in Figure 29 described in Table 10.

  • Page 41: Important Notice

    IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

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