Global Control Register (Gblctl) - Texas Instruments TMS320C6000 DSP Reference Manual

Registers
4.1.9

Global Control Register (GBLCTL)

The global control register (GBLCTL) provides initialization of the transmit and
receive sections. The GBLCTL is shown in Figure 4–9 and described in
Table 4–11.
The bit fields in GBLCTL are synchronized and latched by the corresponding
clocks (ACLKX for bits 12–8 and ACLKR for bits 4–0). Before GBLCTL is pro-
grammed, you must ensure that serial clocks are running. If the corresponding
external serial clocks, ACLKX and ACLKR, are not yet running, you should se-
lect the internal serial clock source in AHCLKXCTL, AHCLKRCTL,
ACLKXCTL, and ACLKRCTL before GBLCTL is programmed. Also, after pro-
gramming any bits in GBLCTL you should not proceed until you have read
back from GBLCTL and verified that the bits are latched in GBLCTL.
Figure 4–9. Global Control Register (GBLCTL) [Offset 0044h]
31
15
†
Reserved
R-0
7
†
Reserved
R-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
† If writing to this field, always write the default value for future device compatibility.
Table 4–11. Global Control Register (GBLCTL) Field Descriptions
†
Bit field symval
31–13 Reserved –
12 XFRST
RESET
ACTIVE
† For CSL implementation, use the notation MCASP_GBLCTL_field_symval
4-22 Registers
†
Reserved
R-0
13 12 11
XFRST XSMRST
R/W-0 R/W-0
5 4 3
RFRST RSMRST
R/W-0 R/W-0
†
Value Description
0 Reserved. The reserved bit location always returns the default
value. A value written to this field has no effect. If writing to this
field, always write the default value for future device
compatibility.
Transmit frame sync generator reset enable bit.
0 Transmit frame sync generator is reset.
1 Transmit frame sync generator is active. When released from
reset, the transmit frame sync generator begins counting serial
clocks and generating frame sync as programmed.
10 9
XSRCLR XHCLKRST
R/W-0 R/W-0
2 1
RSRCLR RHCLKRST
R/W-0 R/W-0
16
8
XCLKRST
R/W-0
0
RCLKRST
R/W-0
SPRU041C