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Texas Instruments TMS320DM36 Series Manuals
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Texas Instruments TMS320DM36 Series manuals available for free PDF download: User Manual
Texas Instruments TMS320DM36 Series User Manual (134 pages)
Digital Media System-on-Chip (DMSoC), Ethernet Media Access Controller (EMAC)
Brand:
Texas Instruments
| Category:
IP Access Controllers
| Size: 0.68 MB
Table of Contents
Table of Contents
3
Preface
10
Introduction
13
Purpose of the Peripheral
13
Features
13
Functional Block Diagram
14
EMAC and MDIO Block Diagram
14
Industry Standard(S) Compliance Statement
15
Architecture
15
Clock Control
15
Memory Map
16
Signal Descriptions
16
Ethernet Configuration MII Connections
16
Pin Multiplexing
17
EMAC and MDIO Signals for MII Interface
17
Ethernet Protocol Overview
18
Ethernet Frame Format
18
Ethernet Frame Description
18
Programming Interface
19
Basic Descriptor Format
19
Typical Descriptor Linked List
20
Basic Descriptor Description
20
Transmit Buffer Descriptor Format
23
Receive Buffer Descriptor Format
26
EMAC Control Module
30
EMAC Control Module Block Diagram
30
MDIO Module
33
MDIO Module Block Diagram
33
EMAC Module
37
EMAC Module Block Diagram
37
Media Independent Interface (MII)
40
2.11 Packet Receive Operation
44
Receive Frame Treatment Summary
47
Middle of Frame Overrun Treatment
48
2.12 Packet Transmit Operation
49
2.13 Receive and Transmit Latency
49
2.14 Transfer Node Priority
50
2.15 Reset Considerations
50
2.16 Initialization
51
2.17 Interrupt Support
55
EMAC Control Module Interrupt Logic Diagram
55
2.18 Power Management
59
2.19 Emulation Considerations
59
Emulation Control
59
EMAC Control Module Registers
60
EMAC Control Module Identification and Version Register (CMIDVER)
60
EMAC Control Module Identification and Version Register (CMIDVER) Field Descriptions
60
EMAC Control Module Software Reset Register (CMSOFTRESET)
61
EMAC Control Module Emulation Control Register (CMEMCONTROL)
61
EMAC Control Module Software Reset Register (CMSOFTRESET) Field Descriptions
61
EMAC Control Module Emulation Control Register (CMEMCONTROL) Field Descriptions
61
EMAC Control Module Interrupt Control Register (CMINTCTRL)
62
EMAC Control Module Interrupt Control Register (CMINTCTRL) Field Descriptions
62
EMAC Control Module Receive Threshold Interrupt Enable Register (CMRXTHRESHINTEN)
63
EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)
63
EMAC Control Module Receive Threshold Interrupt Enable Register (CMRXTHRESHINTEN) Field Descriptions
63
EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN) Field Descriptions
63
EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN)
64
EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) Field Descriptions
64
EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN)
65
EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN) Field Descriptions
65
EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT)
66
EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT)
66
EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT) Field Descriptions
66
EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT) Field Descriptions
66
EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT)
67
EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) Field Descriptions
67
EMAC Control Module Miscellaneous Interrupt Status Register (EWMISCSTAT)
68
EMAC Control Module Miscellaneous Interrupt Status Register (CMMISCINTSTAT)
68
EMAC Control Module Miscellaneous Interrupt Status Register (CMMISCINTSTAT) Field Descriptions
68
EMAC Control Module Receive Interrupts Per Millisecond Register (CMRXINTMAX)
69
EMAC Control Module Transmit Interrupts Per Millisecond Register (CMTXINTMAX)
69
EMAC Control Module Receive Interrupts Per Millisecond Register (CMRXINTMAX) Field Descriptions
69
EMAC Control Module Transmit Interrupts Per Millisecond Register (CMTXINTMAX) Field Descriptions
69
MDIO Registers
70
MDIO Version Register (VERSION)
70
Management Data Input/Output (MDIO) Registers
70
MDIO Version Register (VERSION) Field Descriptions
70
MDIO Control Register (CONTROL)
71
MDIO Control Register (CONTROL) Field Descriptions
71
PHY Acknowledge Status Register (ALIVE)
72
PHY Link Status Register (LINK)
72
PHY Acknowledge Status Register (ALIVE) Field Descriptions
72
PHY Link Status Register (LINK) Field Descriptions
72
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)
73
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions
73
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
74
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions
74
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)
75
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions
75
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
76
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions
76
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
77
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions
77
MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
78
MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field Descriptions
78
MDIO User Access Register 0 (USERACCESS0)
79
MDIO User Access Register 0 (USERACCESS0) Field Descriptions
79
MDIO User PHY Select Register 0 (USERPHYSEL0)
80
MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions
80
MDIO User Access Register 1 (USERACCESS1)
81
MDIO User Access Register 1 (USERACCESS1) Field Descriptions
81
MDIO User PHY Select Register 1 (USERPHYSEL1)
82
MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions
82
Ethernet Media Access Controller (EMAC) Registers
83
Transmit Identification and Version Register (TXIDVER)
86
Transmit Control Register (TXCONTROL)
86
Transmit Identification and Version Register (TXIDVER) Field Descriptions
86
Transmit Control Register (TXCONTROL) Field Descriptions
86
Transmit Teardown Register (TXTEARDOWN)
87
Transmit Teardown Register (TXTEARDOWN) Field Descriptions
87
Receive Identification and Version Register (RXIDVER)
88
Receive Identification and Version Register (RXIDVER) Field Descriptions
88
Receive Control Register (RXCONTROL)
89
Receive Teardown Register (RXTEARDOWN)
89
Receive Control Register (RXCONTROL) Field Descriptions
89
Receive Teardown Register (RXTEARDOWN) Field Descriptions
89
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)
90
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions
90
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
91
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions
91
Transmit Interrupt Mask Set Register (TXINTMASKSET)
92
Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions
92
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)
93
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions
93
MAC Input Vector Register (MACINVECTOR)
94
MAC End of Interrupt Vector Register (MACEOIVECTOR)
94
MAC Input Vector Register (MACINVECTOR) Field Descriptions
94
MAC End of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions
94
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
95
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions
95
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
96
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions
96
Receive Interrupt Mask Set Register (RXINTMASKSET)
97
Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions
97
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
98
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions
98
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
99
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
99
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions
99
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions
99
MAC Interrupt Mask Set Register (MACINTMASKSET)
100
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
100
MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions
100
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions
100
Descriptions
100
Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)
101
Receive Unicast Enable Set Register (RXUNICASTSET)
104
Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions
104
Receive Unicast Clear Register (RXUNICASTCLEAR)
105
Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions
105
Receive Maximum Length Register (RXMAXLEN)
106
Receive Buffer Offset Register (RXBUFFEROFFSET)
106
Receive Maximum Length Register (RXMAXLEN) Field Descriptions
106
Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions
106
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
107
Receive Channel 0-7 Flow Control Threshold Register (Rxnflowthresh)
107
Receive Channel N Flow Control Threshold Register (Rxnflowthresh)
107
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions
107
Receive Channel N Flow Control Threshold Register (Rxnflowthresh) Field Descriptions
107
Receive Channel 0-7 Free Buffer Count Register (Rxnfreebuffer)
108
Receive Channel N Free Buffer Count Register (Rxnfreebuffer)
108
Receive Channel N Free Buffer Count Register (Rxnfreebuffer) Field Descriptions
108
MAC Control Register (MACCONTROL)
109
MAC Control Register (MACCONTROL) Field Descriptions
109
MAC Status Register (MACSTATUS)
111
MAC Status Register (MACSTATUS) Field Descriptions
111
Emulation Control Register (EMCONTROL)
113
FIFO Control Register (FIFOCONTROL)
113
Emulation Control Register (EMCONTROL) Field Descriptions
113
FIFO Control Register (FIFOCONTROL) Field Descriptions
113
MAC Configuration Register (MACCONFIG)
114
Soft Reset Register (SOFTRESET)
114
MAC Configuration Register (MACCONFIG) Field Descriptions
114
Soft Reset Register (SOFTRESET) Field Descriptions
114
MAC Source Address Low Bytes Register (MACSRCADDRLO)
115
MAC Source Address High Bytes Register (MACSRCADDRHI)
115
MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions
115
MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions
115
MAC Hash Address Register 1 (MACHASH1)
116
MAC Hash Address Register 2 (MACHASH2)
116
MAC Hash Address Register 1 (MACHASH1) Field Descriptions
116
MAC Hash Address Register 2 (MACHASH2) Field Descriptions
116
Back off Test Register (BOFFTEST)
117
Transmit Pacing Algorithm Test Register (TPACETEST)
117
Back off Random Number Generator Test Register (BOFFTEST)
117
Back off Test Register (BOFFTEST) Field Descriptions
117
Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions
117
Receive Pause Timer Register (RXPAUSE)
118
Transmit Pause Timer Register (TXPAUSE)
118
Receive Pause Timer Register (RXPAUSE) Field Descriptions
118
Transmit Pause Timer Register (TXPAUSE) Field Descriptions
118
MAC Address Low Bytes Register (MACADDRLO)
119
MAC Address Low Bytes Register (MACADDRLO) Field Descriptions
119
MAC Address High Bytes Register (MACADDRHI)
120
MAC Index Register (MACINDEX)
120
MAC Address High Bytes Register (MACADDRHI) Field Descriptions
120
MAC Index Register (MACINDEX) Field Descriptions
120
Transmit Channel 0-7 DMA Head Descriptor Pointer Register (Txnhdp)
121
Receive Channel 0-7 DMA Head Descriptor Pointer Register (Rxnhdp)
121
Transmit Channel N DMA Head Descriptor Pointer Register (Txnhdp)
121
Receive Channel N DMA Head Descriptor Pointer Register (Rxnhdp)
121
Transmit Channel N DMA Head Descriptor Pointer Register (Txnhdp) Field Descriptions
121
Receive Channel N DMA Head Descriptor Pointer Register (Rxnhdp) Field Descriptions
121
Transmit Channel 0-7 Completion Pointer Register (Txncp)
122
Receive Channel 0-7 Completion Pointer Register (Rxncp)
122
Transmit Channel N Completion Pointer Register (Txncp)
122
Receive Channel N Completion Pointer Register (Rxncp)
122
Transmit Channel N Completion Pointer Register (Txncp) Field Descriptions
122
Receive Channel N Completion Pointer Register (Rxncp) Field Descriptions
122
5.50 Network Statistics Registers
123
Statistics Register
123
Appendix A Glossary
131
Physical Layer Definitions
132
Appendix B Revision History
133
Document Revision History
133
Important Notice
134
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Texas Instruments TMS320DM36 Series User Manual (86 pages)
Brand:
Texas Instruments
| Category:
Recording Equipment
| Size: 0.39 MB
Table of Contents
Table of Contents
3
Preface
7
Introduction
10
Purpose of the Peripheral
10
Features
10
Functional Block Diagram
11
Industry Standard Compliance Statement
11
Mcbsp Block Diagram
11
Peripheral Architecture
12
Clock Control
12
Signal Descriptions
12
Pin Multiplexing
12
Endianness Considerations
12
Mcbsp Interface Signals
12
Clock, Frames, and Data
13
Clock and Frame Generation
13
Transmit Data Clocking
14
Receive Data Clocking
14
Sample Rate Generator Block Diagram
15
Choosing an Input Clock for the Sample Rate Generator with the SCLKME and CLKSM Bits
16
CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV
18
CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV
19
Digital Loopback Mode
19
Receive Clock Selection
20
Transmit Clock Selection
21
Programmable Frame Period and Width
22
Receive Frame Synchronization Selection
22
Transmit Frame Synchronization Selection
22
Dual-Phase Frame Example
24
RCR/XCR Fields Controlling Elements Per Frame and Bits Per Element
24
Receive/Transmit Frame Length Configuration
24
Single-Phase Frame of Four 8-Bit Elements
25
Receive/Transmit Element Length Configuration
25
Single-Phase Frame of One 32-Bit Element
26
Data Delay
26
Effect of RJUST Bit Values with 12-Bit Example Data Abch
27
Effect of RJUST Bit Values with 20-Bit Example Data Abcdeh
27
Mcbsp Standard Operation
28
Receive Operation
29
Transmit Operation
29
Maximum Frame Frequency for Transmit and Receive
30
Unexpected Frame Synchronization with (R/X)FIG
31
Unexpected Frame Synchronization with (R/X)FIG
32
Maximum Frame Frequency Operation with 8-Bit Data
33
Data Packing at Maximum Frame Frequency with (R/X)FIG
33
Serial Port Receive Overrun
35
Serial Port Receive Overrun Avoided
35
Decision Tree Response to Receive Frame Synchronization Pulse
37
Unexpected Receive Frame Synchronization Pulse
37
Transmit with Data Overwrite
38
Transmit Empty
39
Transmit Empty Avoided
39
Μ-Law/A-Law Companding Hardware Operation
41
Decision Tree Response to Transmit Frame Synchronization Pulse
41
Unexpected Transmit Frame Synchronization Pulse
41
Companding Flow
42
Companding Data Formats
42
Transmit Data Companding Format in DXR
42
Justification of Expanded Data in DRR
42
Companding of Internal Data
43
Multichannel Selection Modes
44
DX Timing for Multichannel Operation
45
Receive Channel Assignment and Control When Two Receive Partitions Are Used
46
Transmit Channel Assignment and Control When Two Transmit Partitions Are Used
46
Alternating between the Channels of Partition a and the Channels of Partition B
47
Reassigning Channel Blocks Throughout a Mcbsp Data Transfer
47
Mcbsp Data Transfer in the 8-Partition Mode
48
Receive Channel Assignment and Control When Eight Receive Partitions Are Used
48
Transmit Channel Assignment and Control When Eight Transmit Partitions Are Used
48
Selecting a Transmit Multichannel Selection Mode with the XMCM Bits
49
Activity on Mcbsp Pins for the Possible Values of XMCM
51
SPI Operation Using the Clock Stop Mode
52
Typical SPI Interface
52
Bits Used to Enable and Configure the Clock Stop Mode
53
Effects of CLKSTP and CLKXP Bits on the Clock Scheme
53
SPI Transfer with CLKSTP = 2H (no Clock Delay) and CLKXP
54
SPI Transfer with CLKSTP = 3H (Clock Delay) and CLKXP
54
SPI Transfer with CLKSTP = 2H (no Clock Delay) and CLKXP
55
SPI Transfer with CLKSTP = 3H (Clock Delay) and CLKXP
55
Mcbsp as the SPI Master
57
Bit Values Required to Configure the Mcbsp as an SPI Master
57
2.10 Resetting the Serial Port: RRST, XRST, GRST, and RESET
59
Reset State of Mcbsp Pins
59
2.11 Mcbsp Initialization Procedure
60
Receiver Clock and Frame Configurations
60
Transmitter Clock and Frame Configurations
60
2.12 Interrupt Support
64
2.13 EDMA Event Support
65
2.14 Power Management
66
2.15 Emulation Considerations
66
Mcbsp Emulation Modes Selectable with the FREE and SOFT Bits of SPCR
66
Registers
67
Mcbsp Registers
67
Data Receive Register (DRR)
68
Data Transmit Register (DXR)
68
Data Receive Register (DRR) Field Descriptions
68
Data Transmit Register (DXR) Field Descriptions
68
Serial Port Control Register (SPCR)
69
Serial Port Control Register (SPCR) Field Descriptions
69
Receive Control Register (RCR)
71
Receive Control Register (RCR) Field Descriptions
71
Transmit Control Register (XCR)
73
Transmit Control Register (XCR) Field Descriptions
73
Sample Rate Generator Register (SRGR)
75
Sample Rate Generator Register (SRGR) Field Descriptions
75
Multichannel Control Register (MCR)
76
Multichannel Control Registers (MCR)
76
Multichannel Control Register (MCR) Field Descriptions
76
Enhanced Receive Channel Enable Registers (RCERE0-RCERE3)
80
Enhanced Receive Channel Enable Register N (Rceren)
80
Enhanced Receive Channel Enable Register N (Rceren) Field Descriptions
80
Use of the Receive Channel Enable Registers
81
Enhanced Transmit Channel Enable Registers (XCERE0-XCERE3)
82
Enhanced Transmit Channel Enable Register N (Xceren)
82
Enhanced Transmit Channel Enable Register N (Xceren) Field Descriptions
82
Use of the Transmit Channel Enable Registers
83
Pin Control Register (PCR)
84
Pin Control Register (PCR) Field Descriptions
84
Appendix A Revision History
86
Document Revision History
86
Texas Instruments TMS320DM36 Series User Manual (63 pages)
Digital Media System-on-Chip DMSoC Power Management and Real-Time Clock Subsystem PRTCSS
Brand:
Texas Instruments
| Category:
Single board computers
| Size: 0.38 MB
Table of Contents
Table of Contents
3
Preface
7
Purpose of the PRTC Subsystem
10
Features of the PRTCSS
10
Signal Descriptions
10
PRTCSS Signals
10
Configuration of PRTCSS and PRTCIF
11
PRTCSS Reset and Configuration
11
Normal Mode
11
PRTC Subsystem Block Diagram
11
PRTCSS Configuration Bus Masters and Slaves
11
PRTCSS Initialization Sequence in Normal Mode
12
PRTCSS Initialization Sequence - Normal Mode
12
External Reset Mode
13
Industry Standards Compliance Statement
13
Interrupt Support
13
Clock Controller
13
Clock Source Selection
13
PRTCSS External Circuit Example for Normal Mode
13
Clock Controller
14
EDMA Event Support
14
Emulation Considerations
14
PRTC Interface (PRTCIF)
14
Features of the PRTC Interface
14
PRTC Interface Functional Operation
14
PRTCIF Functional Diagram
14
Flow of the PRTCIF Function
15
Interrupt Status of PRTCSS Events
16
PRTCIF Function Flow
16
PRTCSS Modules
17
General Purpose I/O (GIO)
17
Using the GIO Signal as an Output or Input
17
Configuring a GIO Input Signal
17
Configuring a GIO Output Signal
17
Configuring GIO Interrupt Edge Triggering
18
GIO Interrupt Status
18
Using the PWCTRO2 Signal as a Clock or PWM Output Function
18
Configuring PWCTRO2 Signal as Clock Output
18
Configuring PWCTRO2 Signal as PWM Output Function
18
PWM Output Width
18
Prtcss Intc
19
GO2 PWM Output Period
19
Configuring the INTC Interrupt
20
INTC Interrupt Status
20
Real Time Clock (RTC)
20
RTC Functional Block Diagram
20
Initializing the Timer
21
RTC Initialization
21
RTC Functional Block Diagram
21
Initializing the Watchdog Timer
22
Initializing the Calendar with Alarm
22
Sequencer
23
Sequencer Features
23
Alarm Interrupt Diagram
23
RTC Alarm Enable Bits
23
Initial Sequencer Flow in Normal Mode
24
Sequencer Initial Program Flow in Normal Mode
24
Registers
25
PRTC Interface (PRTCIF) Registers
25
PRTCIF Peripheral ID (PID) Register
26
PRTCIF Peripheral ID Register (PID)
26
PRTCIF Peripheral ID Register (PID) Field Descriptions
26
PRTCIF Control (PRTCIF_CTRL) Register
27
PRTCIF Control (PRTCIF_CTRL) Field Descriptions
27
PRTCIF Access Lower Data (PRTCIF_LDATA) Register
28
PRTCIF Access Lower Data (PRTCIF_LDATA) Field Descriptions
28
PRTCIF Access Upper Data (PRTCIF_UDATA) Register
29
PRTCIF Access Upper Data (PRTCIF_UDATA) Field Descriptions
29
PRTCIF Interrupt Enable (PRTCIF_INTEN) Register
30
PRTCIF Interrupt Enable (PRTCIF_INTEN) Field Descriptions
30
PRTCIF Interrupt Flag (PRTCIF_INTFLG) Register
31
PRTCIF Interrupt Enable (PRTCIF_INTFLG) Register
31
PRTCIF Interrupt Flag (PRTCIF_INTFLG) Field Descriptions
31
Power Management and Real Time Clock Subsystem (PRTCSS) Registers
32
Global Output Pin Output Data (GO_OUT) Register
33
Global Output Pin Output Data (GO_OUT) Field Descriptions
33
Global Input/Output Pin Output Data (GIO_OUT) Register
34
Global Input/Output Pin Output Data (GIO_OUT) Field Descriptions
34
Global Input/Output Pin Direction (GIO_DIR) Register
35
Global Input/Output Pin Direction (GIO_DIR) Field Descriptions
35
Global Input/Output Pin Input Data (GIO_IN) Register
36
Global Input/Output Pin Input Data (GIO_IN) Field Descriptions
36
Global Input/Output Pin Function (GIO_FUNC) Register
37
Global Input/Output Pin Function (GIO_FUNC) Field Descriptions
37
GIO Rise Interrupt Enable (GIO_RISE_INT_EN) Register
38
GIO Rise Interrupt Enable (GIO_RISE_INT_EN) Field Descriptions
38
GIO Fall Interrupt Enable (GIO_FALL_INT_EN) Register
39
GIO Fall Interrupt Enable Register (GIO_FALL_INT_EN)
39
GIO Fall Interrupt Enable Register (GIO_FALL_INT_EN) Field Descriptions
39
GIO Rise Interrupt Flag (GIO_RISE_INT_FLG) Register
40
GIO Rise Interrupt Flag (GIO_RISE_INT_FLG) Field Descriptions
40
GIO Fall Interrupt Flag (GIO_FALL_INT_FLG) Register
41
GIO Fall Interrupt Flag (GIO_FALL_INT_FLG) Field Descriptions
41
EXT Interrupt Enable 0 (INTC_EXTENA0) Register
42
EXT Interrupt Enable 0 (INTC_EXTENA0) Field Descriptions
42
EXT Interrupt Enable 1 (INTC_EXTENA1) Register
43
EXT Interrupt Enable 1 (INTC_EXTENA1) Field Descriptions
43
Event Interrupt Flag 0 (INTC_FLG0) Register
44
Event Interrupt Flag 0 (INTC_FLG0) Field Descriptions
44
Event Interrupt Flag 1 (INTC_FLG1) Register
45
Event Interrupt Flag 1 (INTC_FLG1) Field Descriptions
45
RTC Control (RTC_CTRL) Register
46
RTC Control (RTC_CTRL) Field Descriptions
46
Watchdog Timer Counter (RTC_WDT) Register
47
RTC Watchdog Timer Counter (RTC_WDT) Register
47
RTC Watchdog Timer Counter (RTC_WDT) Field Descriptions
47
Timer Counter 0 (RTC_TMR0) Register
48
Timer Counter 0 (RTC_TMR0) Field Descriptions
48
Timer Counter 1 (RTC_TMR1) Register
49
Timer Counter 1 (RTC_TMR1) Field Descriptions
49
RTC Calendar Control (RTC_CCTRL) Register
50
RTC Calendar Control (RTC_CCTRL) Field Descriptions
50
RTC Seconds (RTC_SEC) Register
51
RTC Seconds (RTC_SEC) Field Descriptions
51
RTC Minutes (RTC_MIN) Register
52
RTC Minutes (RTC_MIN) Field Descriptions
52
RTC Hours (RTC_HOUR) Register
53
RTC Hours Register (RTC_HOUR)
53
RTC Hours (RTC_HOUR) Field Descriptions
53
RTC Days[7:0] (RTC_DAY0) Register
54
RTC Days[7:0] (RTC_DAY0) Field Descriptions
54
RTC Days[14:8] (RTC_DAY1) Register
55
RTC Days[14:8] (RTC_DAY1) Field Descriptions
55
RTC Minutes Alarm (RTC_AMIN) Register
56
RTC Minutes Alarm (RTC_AMIN) Field Descriptions
56
RTC Hours Alarm (RTC_AHOUR) Register
57
RTC Hours Alarm (RTC_AHOUR) Field Descriptions
57
RTC Days[7:0] Alarm (RTC_ADAY0) Register
58
RTC Days[7:0] Alarm (RTC_ADAY0) Field Descriptions
58
RTC Days[14:8] Alarm (RTC_ADAY1) Register
59
RTC Days[14:8] Alarm (RTC_ADAY1) Field Descriptions
59
Clock Control (CLKC_CNT) Register
60
Clock Control (CLKC_CNT) Field Descriptions
60
Sequencer Loop Counter Value (SEQ_LOOP) Register
61
Sequencer Loop Counter Value (SEQ_LOOP) Field Descriptions
61
Appendix A Revision History
62
Changes Made in this Revision
62
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