Reset - Quectel 5G Module Series Hardware Design

3.6. Reset

RESET# is an asynchronous and active LOW signal (1.5 V logic level). Whenever this pin is active, the
module will immediately enter Power On Reset (POR) condition.
Please note that triggering the RESET# signal will lead to loss of all data in the modem and removal of
system drivers. It will also disconnect the modem from the network.
Table 12: Definition of RESET# Pin
Pin No. Pin Name
67 RESET#
The module can be reset by pulling down the RESET# pin for 250–600 ms. An open collector/drain driver
or a button can be used to control the RESET# pin.
Host
GPIO
Figure 12: Reference Circuit of RESET# with NPN Driver Circuit
RM500Q-AE&RM502Q-AE_Hardware_Design
I/O Description
Reset the module.
DI, PU
Active LOW
Reset pulse
R2
1k
100k
RM500Q-AE&RM502Q-AE Hardware Design
DC Characteristics
V max = 1.575 V
IH
V min = 1.25V
IH
V max = 0.45V
IL
RESET#
Q1
NPN
R3
250-600 ms
5G Module Series
Comment
Internally pulled up to
1.5 V with a 100 kΩ
resistor.
Module
VDD 1.5V
R1
100k
67
PMIC
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