FIC VT-502 Manual page 50

16 Bit I/O Recovery Time
Allows you to set the 16-bit ISA I/O recovery time.
The options are: 1 (Default), 2, 3, 4. Unit: Bus clock.
Memory Hole At 15M-16M
When enabled, the memory hole at the 15MB address will be relocated to the
15~16MB address range of the ISA cycle when the processor accesses the
15~16MB address area.
When disabled, the memory hole at the 15MB address will be treated as a
DRAM cycle when the processor accesses the 15~16MB address area.
The options are: Enabled, Disabled (Default).
Peer Concurrency
Enable this item to allow the processor to continue its operation while
another PCI Bus is active.
The options are: Enabled (Default), Disabled.
Delayed PCI Transaction
Enable this feature to abort the current CPI master cycle and to accept the
new PCI master request, it reaccepts the original PCI master and returns the
PCI data phase to the original PCI master.
The options are: Disabled (default), Enabled.
Award BIOS Setup
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