FIC VT-502 Manual page 49

VT-502 Mainboard Manual
DRAM Write Burst Timing
Allows you to define DRAM write burst timing.
The options are: X-3-3-3, X-2-2-2, X-4-4-4.
Fast MA to RAS# Delay CLK
Allows you to select the clock of the memory address (MA) to RAS# delay.
This feature is for technician use. The options are: 1, 2.
Fast EDO Path Select
When enabled, it allows you to select a fast path for CPU to DRAM read
cycles for the leadoff. This is valid for EDO DRAMs only.
The options are: Disabled, Enabled.
Refresh RAS# Aassertion
This feature allows you to control the number of clocks RAS# is asserted for
Refresh cycles.
The options are: 4 Clks, 5 Clks.
SDRAM (CAS Lat/RAS-to-CAS)
If you install a DIMM, this feature allows you to select the ratio of CAS
Latency to RAS-to-CAS. The default setting is slowest. The 2|3/4/7 is
fastest. The second one is 2|3/5/8, then is 3|3/4/7.
The options are: 3|3/5/8 (Default), 3|3/4/7, 2|3/5/8, 2|3/4/7.
System BIOS Cacheable
When enabled, allows the ROM area F000H-FFFFH to be cacheable when
cache controller is activated.
The options are: Disabled (Default), Enabled.
Video BIOS Cacheable
When enabled, allows the system to use the video BIOS codes from SRAMs,
instead of the slower DRAMs or ROMs.
The options are: Enabled (Default), Disabled.
8 Bit I/O Recovery Time
Allows you to set the 8-bit ISA I/O recovery time.
The options are: 1 (Default), 2, 3, 4, 5, 6, 7, 8. Unit: Bus clock.
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