Asic(Spgp); Memory; Flash Memory - Aficio CM-P1 Service Manual

20 July 2005

6.4 ASIC(SPGP)

• ARM946ES
• 32-bit RISC embedded processor core
• 6KB instruction cache and 16KB data cache
• No tightly coupled memory
• Memory protection unit & CP15 control program
• Dual bus architecture for bus traffic distribution
• AMBA high performance bus (AHB)
• System bus with SDRAM
• IEEE1284 compliant parallel port interface
• Printer video controller for LBP engines
• Graphic execution unit for banding support of printer languages
• Printer video controller for LBP engines
• PVC : Printer video controller without RET algorithm
• HPVC : Printer video controller with RET algorithm. (Line Memory & Lookup
Table Memory : 512 x 8 , 4096 x 16)
• Engine controller
• Motor control unit
• Motor speed lookup table memory (128 x 16 x 2)
• Pulse width modulation unit
• 4 channels are supported
• ADC Interface unit
• 3 ADC channels are available
• ADC core (ADC8MUX8) maximum clock frequency :3 MHz
• USB 2.0 interface
• Package :272 pins PBGA
• Power : 1.8V(Core), 3.3V(IO) power operation
• Speed : 166MHz core (ARM946ES) operation, 60MHz bus operation

6.4.1 MEMORY

The machine has flash ROM and DRAM memory units. There are 2 SODIMM
sockets to let extra DRAM or Flash ROM (Postscript Option) to be added.

6.4.2 FLASH MEMORY

• Record/download system program from the PC Interface.
• Fax for journal list
• Memory for one touch dial
• Speed dial list.
• Size : 2M Byte
• Access Time : 70 nsec
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ASIC(SPGP)