SMPS AND HVPS
20 July 2005
4. Developing Voltage (DEV)
• Input voltage : 24 V DC ± 15%
• Output voltage: -200V ~ -600V DC ±20V
• Output voltage fluctuation range: PWM control
• Input contrast of the output stability degree :±5 % or less
• Loading contrast : ± 5 % or less
• Output voltage rise time : 50 ms max
• Output voltage fall time : 50 ms max
• Output loading range : 10MΩ~ 1000 MΩ
• Output control signal (BIAS-PWM) : CPU output is HV output when PWM is low.
5. Supply
• Output voltage :-400 V ~-800V DC ±50 V (ZENER with DEV )
• Input contrast of the output stability degree :under ± 5%
• Loading contrast : ± 5% or less
• Output voltage rise time: 50 ms max
• Output voltage fall time: 50 ms max
• Output loading range: 10 MΩ.~ 1000 MΩ
• Output control signal (BIAS-PWM) : CPU is HV output when PWM is low.
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