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Audio
The audio interface on the EBX-22 is implemented using the VIA VT1708 High Definition
Audio Codec. This interface is AC'97 2.3 compatible. Drivers are available for most Windows-
based operating systems. To obtain the most current versions, consult the EBX-22 product
support page at http://www.versalogic.com/private/Sidewindersupport.asp.
J23 provides the line-level stereo input and line-level stereo output connection points. The
outputs will drive any standard-powered PC speaker set.
S
C
OFTWARE
ONFIGURATION
The audio interface uses PCI interrupt INTB#. The CMOS setup screen is used to select the IRQ
line routed to INTB#.
The audio controller can be disabled within the CMOS setup.
Watchdog Timer
A watchdog timer circuit is included on the EBX-22 that resets the CPU if proper software
execution fails or a hardware malfunction occurs.
E
W
NABLING THE
Bit D7 of the WDSET register (I/O port 1E0h) is used to enable or disable the watchdog from
resetting the CPU on timer expiration. The EXP field (bits D6-D0) of the same register set the
expiration time. The expiration time can be set to a maximum of just under 16 seconds (7Fh) and
a minimum of 1 second (08h). The formula for determining the EXP code is given as:
Seconds x 8 = Decimal Value = Hex Value
For example, for an expiration time of 5.5 seconds:
5.5 x 8 = 44 = 2Ch (written to the EXP field of the WDSET register)
D
W
ISABLING THE
Clearing bit D7 in the WDSET register (at I/O port 1E0h) disables the watchdog timer. No
special procedure is required.
EBX-22 Reference Manual
Table 21: Audio Pinout
CBR-4004
Signal
J23 Pin
J9 Pin
Name
37
2
AUDINR
39
4
AUDINL
40
5
GND
CBR-4004
Signal
J23 Pin
J8 Pin
Name
32
2
AUDOUTR
34
4
AUDOUTL
35
5
GND
ATCHDOG
ATCHDOG
Interfaces and Connectors
Function
Line-In Right
Line-In Left
Ground
Function
Line-Out Right
Line-Out Left
Ground
49
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