Scheme Logic - Toshiba GRL150-100 Series Instruction Manual

2.3.2

Scheme Logic

Figures 2.3.2.1 to 2.3.2.2 show the scheme logic of the phase overcurrent protection OC1 to OC4.
OC1 protection provides selective definite time or inverse time characteristic as shown in Figure
2.3.1.1. The definite time protection is selected by setting [MOC1] to "DT" and trip signal OC1
TRIP is given through the delayed pick-up timer TOC1. The inverse time protection is selected by
setting [MOC1] to any one of "IEC", "IEEE", "US" or "CON" and then setting [MOC1C]
according to the required IDMT characteristic, and trip signal OC1 TRIP is given.
Figure 2.3.2.3 to Figure 2.3.2.4 show the scheme logic of the definite time phase overcurrent
protection OC2 to OC4. The OC2 to OC4 give trip and alarm signals OC2 TRIP, OC3 TRIP and
OC4 ALARM through the delayed pick-up timers TOC2 to TOC4 respectively.
The signal OC1-INST to OC4-INST are available to trip instantaneously for a fault.
The OC1 to OC4 protection can be disabled by the scheme switches [OC1EN] to [OC4EN] or the
binary input signals OC1 BLOCK to OC4 BLOCK respectively.
ICD is the inrush current detector ICD, which detects second harmonic inrush current during
transformer energisation, and can block the OC elements by the scheme switch [OC-ICD]. See
Section 2.10. The logic sequence is configured by the PLC.
Note: For the symbols used in the scheme logic, see Appendix K.
1000.00
100.00
10.00
1.00
0.1
Figure 2.3.1.2 Dependent Time Reset Characteristics
⎯ 23 ⎯
IEEE Reset Curves
(Time Multiplier = 1)
EI
VI
CO8
MI
CO2
Current (Multiple of Setting)
6 F 2 S 0 8 2 8
1