Advanced Chipset Control Submenu - Xycom AHIP6+ Manual

AHIP6+ Manual

Advanced Chipset Control Submenu

Advanced
Advanced Chipset Control
Enable Memory Gap
ECC Config:
SERR Signal Condition:
8-bit I/O Recovery:
16-bit I/O Recovery:
­¯
F1 Help
¨ Select Menu
ESC Exit
This menu allows you to change the values in the chipset registers and
optimize your system's performance.
Most system configurations will work best with these options in their de-
fault configurations. Fast processors (e.g., a 450 MHz Pentium II proces-
sor) may cause I/O failures at the default recovery values. You can in-
crease the number of cycles when encountering this problem; however,
slowing down the clock too much may cause I/O initialization problems.
You should increase the number of clock cycles incrementally, until you
see an improvement in I/O performance.
Option
Enable Memory Gap
ECC Configuration
SERR Signal Conditions
8-bit I/O Recovery
16-bit I/O Recovery
3-8
Xycom BIOS Setup Utility
[Disabled]
[Disabled]
[Multiple bit]
[3.5]
[3.5]
Select Item
Figure 3-7. Advanced Chipset Control Submenu
Table 3-7. Advanced Chipset Control Submenu Options
Description
Allows creation at a 128K memory gap in conventional memory from 512K to 640K, or a
1MB memory gap in extended memory from 15 MB to 16 MB. Requires use of conven-
tional or extended memory. Default is [Disabled].
Allows configuration of Error Checking and Correction Memory. Requires ECC mem-
ory. Default is [Disabled]
Allows configuration of conditions upon which the SERR signal is to be asserted for
ECC memory. Requires ECC memory. Default is [Multiple bit].
Number of ISA clock cycles inserted between back-to-back I/O operations.
-/+ Change Values
Enter Select » Submenu
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F9 Setup Defaults
F10 Save & Exit