Schematic; Figure 12. Power And Decoupling - STMicroelectronics SPC570SADPT100S User Manual

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Schematic

Pow e r a n d De c ou p li n g
1.25V_SR 3.3V_SR 5.0V_SR
J2
1
2
3
4
1437671-6
GND
DUT1A
OSC & JTAG (3.3V or 5V)
I/O (3.3v - 5V)
SPC570SADPT100S
Power Pins
103
EPAD
VELVETY-eTQFP100
GND
GT1 GT2 GT3
TEST2 TEST2 TEST2
Figure 12. Power and decoupling
VREFH_ADC
VDD_HV_ADC_TSENS
29
VREFH_ADC
VDD_HV_PMU_OSC
ADC
39
VDD_HV_ADC_TSENS
55
VDD_HV_PMU_OSC
20
VDD_HV_IO_W0
51
VDD_HV_IO_E0
85
VDD_HV_IO_N0
CLOSE TO
NOT
PIN 20
MOUNTED
95 VDD_HV_IO_MAIN
VDD_HV_IO_N1
C15 C18 C19 C20
C21
100nF 1nF 100nF 1nF DNP
2.2uF
50V 100V 50V 100V
16V
0603 0603 0603 0603
0805
X7R X7R X7R X7R
X7R
GND GND
19
VDD_LV_W0
MCU CORE LOGIC
52
( 1.25V )
VDD_LV_E0
68
VDD_LV_E1
VDD_LV1
VDD_LV2
VDD_LV3
RING -HEADED FOR PROBE HOOK
GT4 GT5
TEST2 TEST2
GND
5.0V_LR
DEFAULT
1-2 CLOSED
R1
2
10R
C1 C2 C3 1/10W
1uF 100nF 1nF 0805
50V 50V 100V
0805 0603 0603
X7R X7R X7R
5.0V_LR
GND
DEFAULT
1-2 CLOSED
2
C4 C5 C6
470nF 100nF 1nF DNP NOT MOUNTED
50V 50V 100V
0805 0603 0603
X7R X7R X7R
GND
VDD_HV_PMU_OSC
2
C7 C8 C9
2.2uF DNP 100nF 1nF
NOT MOUNTED
16V 50V 100V
0805 0603 0603
X7R X7R X7R
GND
VDD_HV_IO_MAIN
NOT NOT
MOUNTED MOUNTED
2
C10 C11 C13 C14
C22 C12 C23
100nF 1nF DNP 100nF 1nF DNP
2.2uF 2.2uF 2.2uF
50V 100V 50V 100V
16V 16V 16V
0603 0603 0603 0603
0805 0805 0805
X7R X7R X7R X7R
X7R X7R X7R
GND GND
PLACE NEAR RELATIVE DECOUPLING
JP2
C31 C32 C33
default CLOSE
2.2uF DNP 100nF 1nF DNP NOT MOUNTED
NOT MOUNTED
16V 50V 100V
0805 0603 0603
X7R X7R X7R
GND
JP4
C28 C29 C30
default CLOSE
NOT MOUNTED
2.2uF DNP 100nF 1nF DNP
NOT MOUNTED
16V 50V 100V
0805 0603 0603
X7R X7R X7R
GND
JP5
default CLOSE
C25 C26 C27
2.2uF 100nF 1nF DNP NOT MOUNTED
16V 50V 100V
0805 0603 0603
X7R X7R X7R
GND
3.3V_SR 5.0V_SR 1.25V_SR
J3
STRIP3PM
J1
STRIP3PM
J5
STRIP3PM
DEFAULT
1-2 CLOSED
J6
STRIP3PM
DEFAULT
1-2 CLOSED
JP1
default OPEN