4
Schematic diagrams
DC-DC Power Supply
J J 1 1
2
C C O O N N 2 2
1
J 1: VDDA ENABLE/ DI SABLE
VDDA
F F 1 1
2 2 A A
D D 3 3
DF01S
C C N N 1 1
1
1
D D 2 2
- -
+ +
2
2
1
2
3
S S M M 4 4 T T 3 3 0 0 C C A A Y Y
3
C C O O N N N N : : D D C C J J A A C C K K
I / P
B B R R I I D D G G E E
12V, 1. 5A
J J 4 4
C C O O N N 2 2
J 4: VDDD ENABLE/ DI SABLE
U U 3 3
VDDD
L L M M 2 2 9 9 3 3 1 1 A A D D T T 5 5 0 0 R R Y Y
VDC
1
3
V V D D D D
VIN
VOUT
C C 2 2 1 1
C C 5 5 3 3
1 1 0 0 0 0 n n F F
1 1 0 0 0 0
µF
LED DRIVER ALED1262ZT
VDDD
C C 2 2 3 3
C C 2 2 4 4
U U 4 4
1 1 0 0 0 0 n n F F
11
µF
A A L L E E D D 1 1 2 2 6 6 2 2 Z Z T T
1
24
VDDD
OUT 0
SDA
R R 2 2 4 4
0 0 E E
2
23
SDA
OUT 1
SCL
R R 2 2 7 7
0 0 E E
3
22
SCL
OUT 2
VDDA
4
21
VDDA
OUT 3
C C 3 3 5 5
C C 3 3 6 6
5
20
LD03
OUT 4
C C 4 4 3 3
R R 2 2 9 9
6
19
REXT
OUT 5
1 1 0 0 0 0 n n F F
11
µF
6 6 . . 2 2 K K
7
18
GND
OUT 6
11
µF
FLAG
R R 3 3 3 3
8
17
FLG
OUT 7
0 0 E E
9
16
GPWM
OUT 8
10
15
PG
OUT 9
11
14
OTP1/2
OUT10
12
13
CS
OUT11
CS1
OTP1/2
FLAG
R R 3 3 7 7
R R 4 4 3 3
VDDA
0 0 E E
4 4 7 7 K K
R R 3 3 8 8
C C 4 4 7 7
1 1 0 0 0 0 K K
1 1 0 0 0 0 n n F F
GPWM
USB-UART BRIDGE Connectors
USB-UART BRIDGE Supply
J 10: UART Br i dge
VDC
J J 9 9
J J 1 1 0 0
Suppor t i ng
U U A A R R T T _ _ C C O O N N N N E E C C T T O O R R
C C O O N N 5 5
Connec t or
GND
4
5
3
UART_TX
4
2
UART_RX
3
+3.3V
1
2
1
Figure 19.
STEVAL-LLL002M1 circuit schematic
Microcontroller
VDC
U U 1 1
VDD
L L 1 1
1 1 8 8
µF
R R 2 2
8
1
VRAIL
VCC
VOUT
1 1 0 0 K K
C C 2 2
1 1 0 0 u u F F
A A 7 7 9 9 8 8 6 6 A A
R R 7 7
C C 2 2 2 2
3
5
EN
FB
2 2 7 7 E E
1 1 0 0 0 0
µ
F F
6
D D 1 1
FSW
S S T T P P S S 3 3 L L 4 4 0 0 - - Y Y
C C 4 4
C C 3 3
3 3 3 3 n n F F
1 1 0 0 0 0
µF
C C 7 7
C C 8 8
1 1 . . 2 2 n n F F
1 1 0 0 u u F F
C C 1 1 0 0
C C 1 1 1 1
C C 1 1 2 2
R R 9 9
R R 1 1 0 0
R R 1 1 1 1
6 6 8 8 0 0 E E
4 4 . . 7 7 K K
2 2 2 2 0 0 K K
C C 1 1 5 5
1 1 0 0 0 0 n n F F
R R 1 1 2 2
1 1 . . 2 2 K K
D D 4 4
VRAIL
D D 5 5
L L E E D D
VDDD
D D 8 8
D D 9 9
L L E E D D
C C 2 2 5 5
C C 2 2 9 9
C C 3 3 0 0
U U 5 5
D D 1 1 2 2
2 2 . . 2 2
µF
1 1 0 0 0 0 n n F F
11 µ F
A A L L E E D D 1 1 2 2 6 6 2 2 Z Z T T
D D 1 1 3 3
L L E E D D
1
24
VDDD
OUT 0
D D 1 1 5 5
SDA
R R 2 2 6 6
0 0 E E
D D 1 1 7 7
2
23
SDA
OUT 1
SCL
L L E E D D
R R 2 2 8 8
0 0 E E
3
22
SCL
OUT 2
D D 2 2 0 0
VDDA
4
21
D D 2 2 1 1
VDDA
OUT 3
L L E E D D
C C 3 3 7 7
C C 3 3 8 8
5
20
LD03
OUT 4
D D 2 2 4 4
C C 4 4 4 4
R R 3 3 0 0
D D 2 2 5 5
6
19
REXT
OUT 5
L L E E D D
1 1 0 0 0 0 n n F F
11
µF
6 6 . . 2 2 K K
7
18
GND
OUT 6
D D 2 2 8 8
11
µF
FLAG
R R 3 3 4 4
D D 2 2 9 9
8
17
FLG
OUT 7
L L E E D D
0 0 E E
9
16
GPWM
OUT 8
D D 3 3 2 2
10
15
D D 3 3 3 3
PG
OUT 9
L L E E D D
11
14
OTP1/2
OUT10
D D 3 3 6 6
D D 3 3 7 7
12
13
CS
OUT11
L L E E D D
D D 4 4 0 0
D D 4 4 1 1
L L E E D D
CS2
D D 4 4 4 4
OTP1/2
D D 4 4 5 5
L L E E D D
OPEN_1_2
D D 4 4 8 8
FLAG
OPEN_2_2
D D 4 4 9 9
L L E E D D
R R 3 3 9 9
R R 4 4 4 4
VDDA
0 0 E E
4 4 7 7 K K
R R 4 4 5 5
C C 4 4 8 8
1 1 0 0 0 0 K K
1 1 0 0 0 0 n n F F
USB-UART BRIDGE Level Shifting
R R 5 5 1 1
3
1
+3.3V
STM8_UART_TX
1 1 K K
UART_TX
VIN
VOUT
C C 5 5 1 1
U U 8 8
C C 5 5 2 2
3 3 3 3 0 0 n n F F
L L 7 7 8 8 L L 3 3 3 3 A A B B U U T T R R
1 1 0 0 0 0 n n F F
R R 5 5 3 3
1 1 . . 8 8 K K
SOT- 89
OTP1/2-Setting-Read
Gl obal PW M f or
Br i ght nes s Cont r ol
R R 1 1
NRST
R R 3 3
4 4 . . 7 7 K K
1 1 0 0 K K
R R 6 6
GPWM
1 1 K K
S S W W 1 1
R R e e s s e e t t
C C 1 1
1 1 0 0 0 0 n n F F
U U 2 2
FLAG
1
24
NRST
PC7
2
23
PA1
PC6
3
22
PA2
PC5
C C 5 5
C C 6 6
4
21
R R 8 8
VSS
PC4
1 1 0 0 0 0 n n F F
1 1 0 0 u u F F
5
S S T T M M 8 8 A A F F 6 6 2 2 6 6 6 6
20
S S 1 1
2 2 . . 2 2 K K
VCAP
PC3
VDD
6
19
C C 9 9
VDD
VDD
PC2
VDD
1 1 0 0 0 0 n n F F
SWIM
7
18
VDDIO
PC1
8
17
PF4
PE5
C C 1 1 3 3
C C 1 1 4 4
NRST
1 1 0 0 u u F F
1 1 0 0 0 0 n n F F
S S W W I I M M _ _ C C o o n n n n e e c c t t o o r r
VDD
R R 1 1 3 3
C C 1 1 6 6
C C 1 1 7 7
1 1 0 0 K K
1 1 0 0 u u F F
1 1 0 0 0 0 n n F F
R R 1 1 4 4
1 1 0 0 K K
R R 1 1 6 6
C C 1 1 8 8
C C 1 1 9 9
R R 1 1 5 5
1 1 0 0 0 0 n n F F
1 1 0 0 0 0 n n F F
P P O O T T _ _ 1 1 0 0 K K
P P O O T T _ _ 1 1 0 0 K K
S S 2 2
C C 2 2 0 0
R R 1 1 7 7
SDA
1 1 0 0 0 0 n n F F
4 4 . . 7 7 K K
R R 1 1 9 9
R R 2 2 0 0
R R 1 1 8 8
SCL
1 1 K K
1 1 K K
4 4 . . 7 7 K K
VRAIL
D D 6 6
VRAIL
L L E E D D
VDDD
L L E E D D
D D 1 1 0 0
L L E E D D
C C 2 2 6 6
C C 3 3 1 1
C C 3 3 2 2
U U 6 6
L L E E D D
C C 2 2 7 7
2 2 . . 2 2
µF
1 1 0 0 0 0 n n F F
11
µF
A A L L E E D D 1 1 2 2 6 6 2 2 Z Z T T
D D 1 1 4 4
2 2 . . 2 2
µF
L L E E D D
L L E E D D
1
24
VDDD
OUT 0
SDA
R R 2 2 5 5
0 0 E E
D D 1 1 8 8
2
23
SDA
OUT 1
SCL
L L E E D D
R R 2 2 2 2
0 0 E E
3
22
L L E E D D
SCL
OUT 2
VDDA
4
21
D D 2 2 2 2
VDDA
OUT 3
L L E E D D
C C 3 3 9 9
C C 4 4 0 0
5
20
L L E E D D
C C 4 4 1 1
LD03
OUT 4
C C 4 4 5 5
R R 3 3 1 1
D D 2 2 6 6
6
19
REXT
OUT 5
L L E E D D
1 1 0 0 0 0 n n F F
11
µF
6 6 . . 2 2 K K
L L E E D D
1 1 0 0 0 0 n n F F
7
18
GND
OUT 6
11
µF
FLAG
R R 3 3 5 5
D D 3 3 0 0
8
17
FLG
OUT 7
L L E E D D
0 0 E E
9
16
L L E E D D
GPWM
OUT 8
10
15
D D 3 3 4 4
PG
OUT 9
L L E E D D
11
14
L L E E D D
OTP1/2
OUT10
D D 3 3 8 8
12
13
CS
OUT11
L L E E D D
L L E E D D
D D 4 4 2 2
L L E E D D
CS3
L L E E D D
OTP1/2
D D 4 4 6 6
L L E E D D
L L E E D D
FLAG
OPEN_3_2
D D 5 5 0 0
L L E E D D
R R 4 4 0 0
R R 4 4 1 1
VDDA
L L E E D D
0 0 E E
4 4 7 7 K K
R R 4 4 6 6
C C 4 4 9 9
1 1 0 0 0 0 K K
1 1 0 0 0 0 n n F F
Mounting Holes
VDD
R R 4 4 9 9
STM8_UART_RX
4 4 . . 7 7 K K
R R 5 5 0 0
1
1
4 4 . . 7 7 K K
M M H H 1 1
M M H H 2 2
R R 5 5 2 2
Q Q 1 1
D D N N M M
B B S S S S 1 1 2 2 3 3
1
G
Q Q 2 2
UART_RX
R R 5 5 4 4
B B S S S S 1 1 2 2 3 3
1
1 1 0 0 0 0 E E
G
R R 5 5 5 5
1 1 0 0 K K
OTP 1/2 Setting
CS of ALED1262ZT
V V D D D D
R R 4 4
R R 5 5
J2: Chip Select
4 4 7 7 K K
4 4 7 7 K K
To program register
during production
1
3
S S W W 2 2
J J 2 2
S S W W _ _ T T _ _ S S P P D D T T
C C O O N N 5 5
2
OTP1/2-Setting-Read
SW2: Stand Alone Mode Output Configuration
CS1
Hight Level Logic 2-1 - SAM_conf_2 register
CS2
1
CS3
Low Level Logic 2-3 - SAM_conf_1 register
CS4
2
3
4
J J 3 3
Jumpers to Simulate Open Circuit
Error Detection
J J 5 5
J J 6 6
J J 7 7
J J 8 8
C C O O N N 2 2
C C O O N N 2 2
C C O O N N 2 2
C C O O N N 2 2
OPEN_1_2
OPEN_2_2
OPEN_3_2
OPEN_4_2
OPEN_1_1
OPEN_2_1
OPEN_3_1
OPEN_4_1
D D 7 7
VRAIL
VDDD
L L E E D D
D D 1 1 1 1
C C 3 3 3 3
C C 3 3 4 4
U U 7 7
L L E E D D
C C 2 2 8 8
1 1 0 0 0 0 n n F F
1 1 u u F F
A A L L E E D D 1 1 2 2 6 6 2 2 Z Z T T
D D 1 1 6 6
2 2 . . 2 2
µF
L L E E D D
1
24
VDDD
OUT 0
SDA
R R 2 2 1 1
0 0 E E
D D 1 1 9 9
2
23
SDA
OUT 1
SCL
R R 2 2 3 3
0 0 E E
3
22
L L E E D D
SCL
OUT 2
VDDA
4
21
D D 2 2 3 3
VDDA
OUT 3
C C 4 4 2 2
5
20
L L E E D D
LD03
OUT 4
C C 4 4 6 6
R R 3 3 2 2
D D 2 2 7 7
6
19
REXT
OUT 5
11
µF
6 6 . . 2 2 K K
L L E E D D
7
18
GND
OUT 6
11
µF
FLAG
R R 3 3 6 6
D D 3 3 1 1
8
17
FLG
OUT 7
0 0 E E
9
16
L L E E D D
GPWM
OUT 8
10
15
D D 3 3 5 5
PG
OUT 9
11
14
L L E E D D
OTP1/2
OUT10
D D 3 3 9 9
12
13
CS
OUT11
L L E E D D
D D 4 4 3 3
CS4
L L E E D D
OTP1/2
D D 4 4 7 7
L L E E D D
FLAG
OPEN_4_2
D D 5 5 1 1
R R 4 4 2 2
R R 4 4 7 7
VDDA
L L E E D D
0 0 E E
4 4 7 7 K K
R R 4 4 8 8
C C 5 5 0 0
1 1 0 0 0 0 K K
1 1 0 0 0 0 n n F F
1
1
M M H H 3 3
M M H H 4 4
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