Key Features In The M5302A Modules - Keysight Technologies M5302A Startup Manual

1 Overview on M5302A PXIe LVDS Digital IO Modules
CAUTION

1.2.1: Key features in the M5302A modules

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Table 2 describes the connectors labeled in
Table 2 M5302A connectors and their description
Label# Description
1* 100-pin, front panel connector, including 28 bidirectional differential I/O channels.
These differential signals are LVDS (meant to drive 100-ohm differential load) and
have a 1.2 Gbps maximum toggle rate. The Digital I/O connector also includes +5V
power that is available to the user to power external interface circuitry (maximum
current load is 0.5A).
2 Eight SMBs are available for instrument triggers or other general purpose I/O signals.
These channels are single-ended with a voltage swing of 0-3.3V when driving High
Impedance loads (the voltage levels at the DUT are halved when connected to a
50-ohm load). These signals can toggle up to 1000MHz.
3 System Link Connector (currently not supported, reserved for future use).
*Use caution when mating high-density connectors to ensure proper
alignment and prevent damage to the contacts.
• Single PXIe slot
• Kintex UltraScale+ FPGA with PathWave FPGA support
• 28 bidirectional LVDS IO channels
• 4 General Purpose IO channels
• 8 Single-ended SMB IO channels
• PathWave Test Sync Executive support
Figure 1.
M5302A PXIe LVDS Digital IO Modules Startup Guide