Keysight Technologies M5302A Startup Manual page 23

Overview on M5302A PXIe LVDS Digital IO Modules 1
The RSP is that portion of the BSP that allows you to control your target
FPGA. It provides an API that you can use to download and verify your
FPGA bit image. You may use the RSP to load design images onto the
hardware and perform simple register and streaming accesses to one or
more sandboxes.
The FPGA design consists of two regions: the static region and the
sandbox region. The static region for each supported module is defined
within BSP and cannot be modified. This region defines the
implementation of the FPGA interfaces to external resources, and defines
the interfaces to the sandbox. A static region implementation can define
one or more sandbox regions in an FPGA design. The sandbox region
contains the user specific FPGA design. The interface of the sandbox
depends on the static region implementation. A specific design flow is
promoted by PathWave FPGA, called Partial Reconfiguration (PR). In a PR
flow, a full FPGA reconfiguration is only necessary once for a given static
region version. The sandboxes can be reconfigured anytime, without a full
reconfiguration, and without stopping the current operation of the FPGA.
To perform FPGA designing, the BSP must be installed on the same
machine as the PathWave FPGA software. Both PathWave FPGA software
and the BSP function together and cannot be used individually.
To control the front panel IO on the M5302A modules, the M5302x API
allows you to control the hardware.
The hardware license option -PWP must be available on the M5302A
NOTE
modules for the implementation of PathWave FPGA BSP.
For installation instructions regarding the PathWave FPGA Board Support
Package, see Installing M5302A BSP on page 69.
For more information regarding the PathWave FPGA interface available for
the Board Support Package corresponding to the M5302A module, refer to
the respective help file embedded in the PathWave FPGA software.
M5302A PXIe LVDS Digital IO Modules Startup Guide 23