Table 22 Lpc Signal Descriptions; Table 23 Spi Interface Signal Descriptions - Congatec COM Express conga-MA5 User Manual

Table 22 LPC Signal Descriptions
Signal Pin # Description
LPC_AD[0:3] B4-B7 LPC multiplexed address, command and data bus
LPC_FRAME# B3 LPC frame indicates the start of an LPC cycle
LPC_DRQ[0:1]# B8-B9 LPC serial DMA request
LPC_SERIRQ A50 LPC serial interrupt
LPC_CLK B10 LPC clock output
Table 23 SPI Interface Signal Descriptions
Signal Pin # Description
SPI_CS# (**) B97 Chip select for carrier board SPI.
SPI_MISO (**) A92 Master Input Slave Output: SPI output data from carrier board
SPI device to module.
SPI_MOSI (**) A95 Master Output Slave Input: SPI output data from module to
carrier board SPI.
SPI_CLK (**) A94 Clock from module to carrier board SPI BIOS flash.
SPI_POWER A91 Power source for carrier board SPI BIOS flash. SPI_POWER shall
be used to power SPI BIOS flash on the carrier only.
BIOS_DIS0# A34 Selection strap to determine the BIOS boot device.
BIOS_DIS1# B88 Selection strap to determine the BIOS boot device. Ground to
select external SPI device. Pull high or leave no-connect to select
on-module BIOS flash
Note
On Intel Apollo Lake SoC, the signals marked with asterisks (**) have native voltage levels that are different from the levels defined in the
COM Express Specification. To comply with the COM Express Specification, the signals are routed through bidirectional level shifters on the
module. The bidirectional level shifters by nature have limited driving strenght. congatec therefore recommends that you route these signals
as short as possible.
Copyright © 2017 congatec AG
I/O PU/PD Comment
I/O 3.3V PU 20k
O 3.3V PU 20k
I 3.3V Not connected
I/O OD 3.3V PU 20k
O 3.3V 25MHz
I/O PU/PD Comment
O 3.3VSB PU 100k
I 3.3VSB
O 3.3VSB PD 100k
O 3.3VSB PD 100k
+ 3.3VSB
I 3.3VSB PU 10k Carrier shall pull to GND or leave no-connect.
3.3VSB
I 3.3VSB PU 10k Carrier shall pull to GND or leave no-connect
3.3VSB
MA50m17 47/60