Gigabit Ethernet; Sata; Usb 2.0 - Congatec Qseven conga-QMX6 User Manual

Nxp i.mx6 arm cortex a9 processor with ultra low power consumption

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5.3

Gigabit Ethernet

The conga-QMX6 rev B.x offers Gigabit Ethernet with the integration of Qualcomm Atheros Gigabit Transceiver. This transceiver is implemented

via the RGMII interface of the i.MX6 processor. The Ethernet interface consists of 4 pairs of low voltage differential pair signals designated from

GBE0_MDI0± to GBE0_MDI3± plus control signals for link activity indicators. These signals can be used to connect to a 10/100/1000 BaseT

RJ45 connector with integrated or external isolation magnetics on the carrier board.

Earlier conga-QMX6 revisions offer Gigabit Ethernet with the integration of Micrel KSZ 9031 Ethernet PHY.

Note

The theoretical maximum performance of 1 Gbps Ethernet is limited to 470 Mbps (total for Tx and Rx) due to internal bus throughput

limitations. The actual measured performance in optimized environment is up to 400 Mbps. For more information, consult NXP's Errata

ERR004512.

Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more

information, refer to section 9.1 "Bootstrap Signals" of this user's guide.

5.4

The NXP

i.MX6 Cortex A9 processor on the conga-QMX6 supports one SATA port only. The supported signals are coupled with 10nF

capacitors and then routed to conga-QMX6 edge finger. The conga-QMX6 offers this SATA port on the MXM connector. This port supports

SATA I (1.5Gbps) and SATA II (3Gbps) and is compliant with SATA specification 3.0, AHCI specification 1.3 and Advanced Microcontroller Bus

Architecture (AMBA) specification 2.0.

Note

SATA interface is only supported on conga-QMX6 quad and dual core variants. Solo core and dual lite variants do not support SATA.

5.5

The conga-QMX6 offers five USB ports via USB 2.0 host controllers provided by the NXP

high performance USB functionality that complies with USB 2.0 specification and with OTG supplement.

The offered ports comprise of one USB OTG port and four USB hosts. These four USB hosts are derived through the integration of an SMSC

USB hub, and are implemented by routing the USB H1 port of the processor to the SMSC Hub. The USB OTG port (OTG client) is connected

directly to the USB_OTG port of the i.MX6 processor.

i.MX6 Cortex A9 processor. These controllers provide

QMX6m12

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