Table of Contents
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header,
3-13
F
FL1 pin, 2-4,
3-4
Flag IO pin, 2-4,
3-15
Flash
EPROM,
3-14
memory, -ix,
2-6
full memory mode,
H
halt loop,
2-8
hardware
debugging,
3-15
design,
3-1
installation,
1-5
restrictions,
A-1
target,
2-14
header
connectors,
3-9
EZ-ICE,
3-13
Help, online,
-xv
host
computer,
3-9
control,
-ix
mode,
3-6
I
IACK ISR,
3-6
ICE
port interface,
3-12
session, 2-12,
A-1
ICNTL register,
2-4
IMASK registers,
2-4
ADSP-2189M EZ-KIT Lite Evaluation System Manual
3-5
input jack,
3-12
see also JP3 connector
inserting breakpoints,
installation tasks,
1-3
installing
hardware,
1-5
licence,
1-6
VisualDSP++ and EZ-KIT Lite
software,
1-5
internal
memory,
3-6
RAM,
2-6
registers,
3-4
SRAM,
2-2
interrupt
button (SW1),
2-16
disabled,
2-5
nesting,
2-5
switch,
3-4
vector, 2-4, 2-8,
A-1
vector table,
2-2
IO
devices,
2-4
IRQE external interrupt, 2-4,
J
J1 (audio in) connector, 1-5,
J2 (audio out) connector, 1-5,
J6 (SPORT1) connector,
JP1 (codec) connector, 2-5, 3-8,
JP2 (codec) connector, 1-5,
JP3 (codec) connector, 1-5, 3-8,
JP4 (line in gain) connector,
JP5 (line in gain) connector,
INDEX
2-15
3-4
3-7
3-7
2-5
3-15
3-8
3-12
3-8
3-8
I-3
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