HP 1660CP Series User Manual page 170

Logic Analyzer Description
The HP 1660CP-series logic analyzers are part of a family of general-
purpose logic analyzers. The HP 1660CP-series consists of four
models ranging in channel width from 34 channels to 136 channels,
with 100-MHz state and 500-MHz timing speeds and a 200 M Vector/s
pattern generator. The HP 1660CP-series logic analyzers are designed
as full-featured standalone or network-configurable instruments for
use by digital and microprocessor hardware and software designers.
All models have HP-IB, RS-232-C, and Centronics interfaces for hard
copy printouts and control by a host computer, and have ethernet
LAN interfaces.
Analyzer memory depth is 4 K per channel in all pod pair groupings,
or 8 K per channel on one pod of a pod pair (half-channel mode).
Pattern generator memory is 258,048 vectors.
Measurement data is displayed as data listings and waveforms, and
can also be plotted on a chart or compared to a reference image.
Profiled data is displayed as histograms of activity by time, state, or
address range.
The 100-MHz state analyzer has master, master/slave, and
demultiplexed clocking modes available. Measurement data can be
stamped with state or time tags. For triggering and data storage, the
state analyzer uses 12 sequence levels with two-way branching,
10 pattern resource terms, 2 range terms, and 2 timers.
The 500-MHz timing analyzer has conventional, transitional, and glitch
timing modes with variable width, depth, and speed selections.
Sequential triggering uses 10 sequence levels with two-way branching,
10 pattern resource terms, 2 range terms, 2 edge terms and 2 timers.
The 200 M Vector/s pattern generator has a memory depth of
258,048 vectors with a maximum of 32 channels of digital stimulus.
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