AXIOMTEK CAPA520 User Manual page 75

8th/ 9th generation intel core processor family 3.5” board
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Register 3: Configuration register.
This register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this
register is cleared, the corresponding port pin is enabled as an output. At reset, the I/Os are
configured as inputs with a weak pull-up to V
Register 3 – Configuration register bit description
Bit
Symbol
Access
7
C7
R/W
6
C6
R/W
5
C5
R/W
4
C4
R/W
3
C3
R/W
2
C2
R/W
1
C1
R/W
0
C0
R/W
Digital I/O
CAPA520 Intel
.
DD
Default Value
Description
1
1
1
Configures the directions of the I/O pins.
1
0 = Corresponding port pin enabled as an output.
1 = Corresponding port pin configured as input
1
(default value).
1
1
1
®
TM
Core
Processor Family 3.5" Board
69

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