Architectural Overview - Atmel AVR ATtiny10 Series Manual

External Clock
To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 4.
Figure 4. External Clock Drive Configuration
External RC Oscillator
For timing insensitive applications, the external RC configuration shown in Figure 5 can be used. For details on how to
choose R and C, see Table 29 on page 53.
Figure 5. External RC Configuration

Architectural Overview

The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single-clock-cycle access
time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands
are output from the register file, the operation is executed, and the result is stored back in the register file – in one clock
cycle.
Two of the 32 registers can be used as a 16-bit pointer for indirect memory access. This pointer is called the Z-pointer, and
can address the register file and the Flash program memory.
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single-register
operations are also executed in the ALU. Figure 2 shows the ATtiny10/11/12 AVR RISC microcontroller architecture. The
AVR uses a Harvard architecture concept with separate memories and buses for program and data memories. The pro-
gram memory is accessed with a two-stage pipelining. While one instruction is being executed, the next instruction is pre-
fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program
memory is reprogrammable Flash memory.
With the relative jump and relative call instructions, the whole 512 address space is directly accessed. All AVR instructions
have a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction.
PB4 (XTAL2)
EXTERNAL
XTAL1
OSCILLATOR
SIGNAL
GND
V
CC
PB4 (XTAL2)
R
XTAL1
C
GND
ATtiny10/11/12
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