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Architectural Overview
The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access
time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands
are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock
cycle.
Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space addressing - enabling
efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table
look up function. These added function registers are the 16-bits X-register, Y-register and Z-register.
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register
operations are also executed in the ALU. Figure 5 shows the AT90S2333/4433 AVR RISC microcontroller architecture.
In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.
This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing
them to be accessed as though they were ordinary memory locations.
Figure 5. The AT90S2333/4433 AVR RISC Architecture
1K/2K X 16
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
AT90S/LS2333 and AT90S/LS4433
6
AVR AT90S2333/4433 Architecture
Program
Counter
Data Bus 8-bit
Status
and Control
32 x 8
General
Purpose
Registrers
ALU
Timer/Counter
Timer/Counter
128 x 8
Data
SRAM
Analog to Digital
128/256 x 8
EEPROM
20
I/O Lines
Interrupt
Unit
SPI
Unit
Serial
UART
8-bit
16-bit
with PWM
Watchdog
Timer
Converter
Analog
Comparator
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