Architectural Overview - Atmel ATmega161 Manual

Architectural
Overview
1228B–09/01
The fast-access register file concept contains 32 x 8-bit general purpose working regis-
ters with a single clock cycle access time. This means that during one single clock cycle,
one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output from
the register file, the operation is executed and the result is stored back in the register file
– in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for
Data Space addressing – enabling efficient address calculations. One of the three
address pointers is also used as the address pointer for the constant table look-up func-
tion. These added function registers are the 16-bit X-register, Y-register and Z-register.
The ALU supports arithmetic and logic functions between registers or between a con-
stant and a register. Single register operations are also executed in the ALU. Figure 4
shows the ATmega161 AVR RISC microcontroller architecture.
Figure 4. The ATmega161 AVR RISC Architecture
8K x 16
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Data Bus 8-bit
Program Status
Counter and Control
32 x 8
General
Purpose
Registers
1024 x 8
Data
SRAM
512 x 8
EEPROM
I/O Lines
ATmega161(L)
Interrupt
ALU
Timer/Counter
with PWM
and RTC
Timer/Counter
with PWM
Timer/Counter
with PWM
Watchdog
32
Comparator
Unit
SPI
Unit
Serial
UART0
Serial
UART1
8-bit
16-bit
8-bit
Timer
Analog
7