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Architectural
Overview
ATmega103(L)
8
Figure 4. The ATmega103(L) AVR RISC Architecture
AVR ATmega103(L) Architecture
64K x 16
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
The AVR uses a Harvard architecture concept – with separate memories and buses for
program and data. The program memory is accessed with a single-level pipeline. While
one instruction is being executed, the next instruction is pre-fetched from the program
memory. This concept enables instructions to be executed in every clock cycle. The pro-
gram memory is In-System Programmable Flash memory. With a few exceptions, AVR
instructions have a single 16-bit word format, meaning that every program memory
address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is
stored on the stack. The stack is effectively allocated in the general data SRAM and,
consequently, the stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The 16-bit stack pointer (SP) is read/write accessible in the
I/O space.
The 4000 bytes data SRAM can be easily accessed through the five different address-
ing modes supported in the AVR architecture.
A flexible interrupt module has its control registers in the I/O space with an additional
global interrupt enable bit in the status register. All the different interrupts have a sepa-
Data Bus 8-bit
Program
Status
Counter
and Test
32 x 8
General
Purpose
Registers
ALU
4K x 8
Data
SRAM
Peripherals
4K x 8
EEPROM
0945G–09/01
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