Audio Headset Jack J1800 (8); Wlan / Bt Antenna Connections (13, 14) - Intrinsyc Open-Q 845 mSOM User Manual

Open-Q™ 845 µSOM Development Kit User Guide
Pi
n Signal
No
GPIO66_CODEC_S
13
PI_MOSI
GPIO67_CODEC_S
15
PI_CLK
GPIO68_CODEC_S
17
PI_CS_N
19 GND
GPIO69_SPKR_I2S
21
_SCK
GPIO70_CODEC_S
23 LIMBUS_CLK_CO
N
GPIO71_CODEC_S
25 LIMBUS_DATA0_
CON
GPIO72_CODEC_S
27 LIMBUS_DATA1_
CON
29 GND
31 MB_VREG_1P8
33 MB_VREG_3P3
35 MB_VREG_5P0
37 DC_IN_12V
39 GND
1. Population option changes are necessary in order to use this signal. See the carrier board
schematic (R-3) for more details.
For more details regarding configuring the GPIOs on this header, refer to the Open-Q 845 Software
Release Notes to determine feature support in the latest software release.

3.7.21 Audio Headset Jack J1800 (8)

In addition to the audio expansion headers, the Open-Q 845 µSOM Development Kit also includes a
standard 3.5mm audio headset jack J1800, which provides connection to headphone, microphone
input and headset detection circuits. See item 8 in Figure 1 for the carrier board location of this
headset jack.

3.7.22 WLAN / BT Antenna Connections (13, 14)

The Open-Q 845 µSOM Development Kit WLAN/BT functionality is based on Qualcomm
WCN3990 chipset. It provides WLAN/Bluetooth in 2x2 MIMO with two spatial streams
© Copyright Intrinsyc Technologies Corporation
Description
CPU GPIO66 – can be configured as
PRI_MI2S_WS (see Note 1 below)
CPU GPIO67 – can be configured as
PRI_MI2S_DATA0 (see Note 1
below)
CPU GPIO68 – can be configured as
PRI_MI2S_DATA1 (see Note 1
below)
Ground
CPU GPIO69 – can be configured as
SPKR_I2S_SCK
CPU GPIO70 – can be configured as
SPKR_I2S_CLK (see Note 1 below)
CPU GPIO71 – can be configured as
SPKR_I2S_DATA_OUT (see Note 1
below)
CPU GPIO72 – can be configured as
SPKR_I2S_WS (see Note 1 below)
Ground
Carrier board switching regulator
+1.8V
Carrier board switching regulator
+3.3V
Carrier board switching regulator
+5.0V
Voltage from DC Power Input
+12.0V
Ground
Pi
n Signal Description
No
LN_BB_CLK
µSOM PMIC baseband clock
14 2_WCD_CO
output (see Note 1 below)
N
16 No net
18 CDC_IN5_P Codec Input 5 Positive
20 CDC_IN5_N Codec Input 5 Negative
22 GND Ground
24 No net
CDC_MIC_B
26 Microphone Bias 1
IAS1
CDC_LDO_ WCD9340 Audio Codec LDO
28
H output
30 No net
32 GND Ground
GPIO54_CO
34 DEC_INT1_ CPU GPIO54 (see Note 1 below)
CON
GPIO53_CO
36 DEC_INT2_ CPU GPIO53 (see Note 1 below)
CON
38 No net
MB_VREG_1 Carrier board switching regulator
40
P8 +1.8V
Version 1.0
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