SMART Embedded Computing MVME7100ET Programmer's Reference Manual page 79

Table A-6
Value
34 (0x22)
35 (0x23)
36 (0x24)
37 (0x25)
38 (0x26)
39 (0x27)
40 (0x28)
41 (0x29)
42 (0x2A)
43 (0x2B)
44 (0x2C)
45 (0x2D)
46 (0x2E)
47 (0x2F)
48 (0x30)
49 (0x31)
50 (0x32)
51 (0x33)
52 (0x34)
53 (0x35)
54 (0x36)
55 (0x37)
56 (0x38)
57 (0x39)
MVME7100ET Single Board Computer Programmer's Reference (6806800K88C)
SPD Contents (continued)
Offset Description
Data Input Setup Time Before Clock (t DS): 0x10 = 0.1ns.
10
Refer to Note
Data Input Hold Time After Clock (t DH): 0x18 = 0.18ns.
18
Refer to Note
3C Write Recovery Time (t WR): 0x3C = 15ns
1E Internal Write to Read Command Delay (t WTR): 0x1E = 7.5ns
1E Internal Read to Precharge Command Delay (t RTP): 0x1E = 7.5ns
00 Reserved
06 Extension of Byte 41 and 42
3C Minimum Active to Active/Auto Refresh Time (t RC) 0x3C = 60ns
Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC)
7F
0x7F = 127.5ns
80 Maximum Cycle Time (t CK max) 0x80 = 8ns
DQS-DQ Skew for DQS and associated DQ signals (t DQSQ max) 0x18
18
= 0.240ns
22 Read Data Hold Skew Factor (t QHS) 0x22 = 0.340ns
00 PLL Relock Time
50 Tcasemax: 0x50 = 95 degree max case temperature
00 Not Used
03 0x03 = Double refresh mode bit and High temperature self-refresh
00 Not Used
00 Not Used
00 Not Used
00 Not Used
00 Not Used
00 Not Used
00 Not Used
00 Not Used
Programmable Configuration Data
3
.
3
.
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