Test Register 2; External Timer Registers; 3.1.24.1 Prescaler - SMART Embedded Computing MVME7100ET Programmer's Reference Manual

3.1.23 Test Register 2

The MVME7100ET provides a second 32-bit test register that reads back the complement
of the data in Test Register 1.
Table 3-24 Test Register 2
REG
BIT
Field
OPER
RESET
TEST2
3.1.24

External Timer Registers

The MVME7100ET provides a set of tick timer registers for access to the four external
timers implemented in the timers/registers PLD. Note that these registers are 32-bit
registers and are not byte writable. The following sections describe the external timer
prescaler and control registers.

3.1.24.1 Prescaler

The Prescaler Adjust value is determined by this formula:
Prescaler Adjust=256-(CLKIN/CLKOUT)
Where CLKIN is the input clock source in MHz and CLKOUT is the desired output clock
reference in MHz.
Table 3-25
REG
BIT
Field
OPER
RESET $E7
MVME7100ET Single Board Computer Programmer's Reference (6806800K88C)
A read from this address will return the complement of the data pattern in
Test Register 1. A write to this address will write the uncomplemented
data to register TEST1.
Prescaler Register
Prescaler Register - 0xF202 0000 (8 bits of a 32-bit register)
7 6
Prescaler Adjust
R/W
Test Register 2 - 0xF200 003C
31:0
TEST2
R/W
FFFF
5 4 3
Register Descriptions
2 1 0
45