SMART Embedded Computing MVME7100ET Programmer's Reference Manual page 52

Programming Details
Table 4-1
MC864xD
Signal
LWE[2:3]
LWE[0]
LGPL3, LGPL5
TSEC2_TXD[4]
TSEC2_TX_ER
TSECn_TXD5
52
MC864xD POR Configuration Settings (continued)
Default
Select
POR
Option
Settings
Control PLD 11
Control PLD 1
Testpoints 11
11
No Connects
(default)
0
Resistors
(pulldowns)
MVME7100ET Single Board Computer Programmer's Reference (6806800K88C)
Description State of Bit vs Function1
00
01
Host/Agent
Config
10
11
0
CPU Boot
Configuration
1
01
Boot Sequencer
10
Configuration
11
01
DDR SDRAM
Type
11
0
eTSEC Width
Configuration
1
Programming Details
SerDesn port is PCIE, then
it is an endpoint.
SerDes2 port is SRIO, then
it is an agent.
SerDes1 port is PCIE, then
it is a root complex.
SerDes2 port is PCIE, then
it is an endpoint.
SerDes2 port is SRIO, then
it is an host.
SerDes1 port is PCIE, then
it is an endpoint.
SerDes2 port is PCIE, then
it is a root complex.
SerDes2 part is SRIO, then
it is an agent.
SerDesn port is PCIE, then
it is a root complex.
SerDes2 part is SRIO, then
it is a host.
CPU boot holdoff mode.
The core 0 is allowed to
boot without waiting for
configuration by an external
master
Normal I2C addressing
Extended I2C addressing
Boot sequencer is disabled
DDR1
DDR2
Ethernet interface operates
in reduced mode, RTBI or
RGMII.
Ethernet interface operates
in standard TBI or GMII
modes.