SMART Embedded Computing MVME7100ET Programmer's Reference Manual page 78

Programmable Configuration Data
Table A-6
Value
17 (0x11)
18 (0x12)
19 (0x13)
20 (0x14)
21 (0x15)
22 (0x16)
23 (0x17)
24 (0x18)
25 (0x19)
26 (0x1A)
27 (0x1B)
28 (0x1C)
29 (0x1D)
30 (0x1E)
31 (0x1F)
32 (0x20)
33 (0x21)
78
SPD Contents (continued)
Offset Description
SDRAM Device Attributes - Number of Banks on SDRAM Device: 0x08 =
8 banks.
08
Refer to Note
SDRAM Device Attributes - CAS Latency: 0x38 = CAS latency 3, 4, and 5.
38
Refer to Note
01 DIMM Mechanical Characteristics
02 DIMM Type Information
00 SDRAM Module Attributes
SDRAM Device Attributes - General: 0x00 = PASR, ODT and Weak
Driver.
07
Refer to Note
Minimum Clock Cycle at CLX-1: 0x3D = 3.75ns.
3D
Refer to Note
Maximum Data Access Time (t AC) from Clock at CLX-1: 0x50 = 0.50ns.
50
Refer to Note
Minimum Clock Cycle at CLX-2: 0x50 = 5.0 Ns.
50
Refer to Note
Maximum Data Access Time (t AC) from Clock at CLX-2: 0x60 = 0.60ns.
60
Refer to Note
Minimum Row Precharge Time (t RP): 0x3C = 15ns.
3C
Refer to Note
Minimum Row Active to Row Active delay (t RRD): 0x1E = 7.5ns.
1E
Refer to Note
Minimum RAS to CAS delay (t RCD): 0x3C = 15ns.
3C
Refer to Note
Minimum RAS Pulse width (t RAS): 0x2D = 45ns.
2D
Refer to Note
01 Module Bank Density: 0x01= 1GB
Address and Command Setup Time Before Clock (t lS): 0x20 = 0.20ns.
20
Refer to Note
Address and Command Hold Time After Clock (t lH): 0x28 = 0.28ns.
28
Refer to Note
MVME7100ET Single Board Computer Programmer's Reference (6806800K88C)
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Programmable Configuration Data