3.1.19 Watch Dog Timer Count Register; Pld Revision Register; Table 3-20 Watch Dog Timer Resolution Register - SMART Embedded Computing MVME7100ET Programmer's Reference Manual

3.1.19 Watch Dog Timer Count Register

The MVME7100ET provides a watch dog timer count register.

Table 3-20 Watch Dog Timer Resolution Register

REG
BIT
Field
OPER
RESET
COUNT
3.1.20

PLD Revision Register

The MVME7100ET provides a PLD revision register that can be read by the system
software to determine the current revision of the timers/registers PLD.
Table 3-21
REG
BIT
Field
OPER
RESET
PLD_REV
MVME7100ET Single Board Computer Programmer's Reference (6806800K88C)
Watch Dog Timer Counter Register - 0xF200 0026
15:0
Count
R/W
03FF
Count. These bits define the watch dog timer count value. When the
watch dog counter is enabled or there is a write to the load register, the
watch dog counter is set to the count value. When enabled the watch dog
counter will decrement at a rate defined by the resolution register. The
counter will continue to decrement until it reaches zero or the software
writes to the load register. If the counter reaches zero a system or board-
level reset will be generated.
PLD Revision Register
PLD Revision Register - 0xF200 0030
7 6 5
PLD_REV
R
01
8-bit field containing the current timer/register PLD revision. The revision
number starts with 01.
Register Descriptions
4 3 2 1 0
43