Table of Contents
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Register Descriptions
Table 3-1
Address
F200 001D
F200 001E
F200 001F
F200 0020
F200 0021
F200 0022
F200 0023
F200 0024
F200 0028
F200 002C
F200 0030
F200 0031
F200 0032
F200 0033
F200 0034
F200 0038
F200 003C
F200 0018 -
F200 0FFF
F201 1000 -
F201 1FFF
F201 2000 -
F201 2FFF
F201 3000 -
F201 3FFF
F201 4000 -
F201 4FFF
26
System I/O Memory Map (continued)
Definition
NAND Flash Chip 2 Status Register
Reserved
Reserved
Watch Dog Timer Load
Reserved
Reserved
Reserved
Watchdog Timer Control (32 bits)
Reserved (32 bits)
Reserved (32 bits)
PLD Revision
Reserved
Reserved
Reserved
PLD Date Code (32 bits)
Test Register 1 (32 bits)
Test Register 2 (32 bits)
Reserved
COM 2 (QUART channel 1)
COM 3 (QUART channel 2)
COM 4 (QUART channel 3)
COM 5 (QUART channel 4)
MVME7100ET Single Board Computer Programmer's Reference (6806800K88C)
Register Descriptions
LBC Bank/Chip
Notes
Select
4
3
4
1
4
1
4
3
4
1
4
1
4
1
4
3
4
1
4
1
4
3
4
1
4
1
4
1
4
3
4
3
4
3
1
5
5
5
5
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